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Texas Instruments CC2541 User Manual

Texas Instruments CC2541
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Stopping DMA Transfers
8.4 Stopping DMA Transfers
Ongoing DMA transfers or armed DMA channels are aborted using the DMAARM register to disarm the
DMA channel.
One or more DMA channels are aborted by writing a 1 to the DMAARM.ABORT register bit, and at the same
time selecting which DMA channels to abort by setting the corresponding DMAARM.DMAARMx bits to 1.
When setting DMAARM.ABORT to 1, the DMAARM.DMAARMx bits for nonaborted channels must be written
as 0.
No DMA interrupt is generated when aborting an ongoing DMA transfer (disarming a DMA channel).
8.5 DMA Interrupts
Each DMA channel can be configured to generate an interrupt to the CPU on completing a DMA transfer.
This is accomplished with the IRQMASK bit in the channel configuration. The corresponding interrupt flag
in the DMAIRQ SFR register is set when the interrupt is generated.
Regardless of the IRQMASK bit in the channel configuration, the corresponding interrupt flag in the
DMAIRQ register is set on DMA channel completion. Thus, software should always check (and clear) this
register when rearming a channel with a changed IRQMASK setting. Failure to do so could generate an
interrupt based on the stored interrupt flag.
If a DMA transfer is aborted prior to its completion, the corresponding bit in the DMAIRQ register is not set,
and an interrupt is not generated.
8.6 DMA Configuration Data Structure
For each DMA channel, the DMA configuration data structure consists of eight bytes. The configuration
data structure is described in Table 8-2.
8.7 DMA Memory Access
The DMA data transfer is affected by endian convention. Note that the DMA descriptors follow big-endian
convention while the other registers follow little-endian convention. This must be accounted for in
compilers.
Table 8-1. DMA Trigger Sources
DMA Trigger
Functional Unit Description
Number Name
0 NONE DMA No trigger, setting the DMAREQ.DMAREQx bit starts transfer.
1 PREV DMA DMA channel is triggered by completion of previous channel.
2 T1_CH0 Timer 1 Timer 1, compare, channel 0
3 T1_CH1 Timer 1 Timer 1, compare, channel 1
4 T1_CH2 Timer 1 Timer 1, compare, channel 2
5 T2_EVENT1 Timer 2 Timer 2, event pulse 1
6 T2_EVENT2 Timer 2 Timer 2, event pulse 2
7 T3_CH0 Timer 3 Timer 3, compare, channel 0
8 T3_CH1 Timer 3 Timer 3, compare, channel 1
9 T4_CH0 Timer 4 Timer 4, compare, channel 0
10 T4_CH1 Timer 4 Timer 4, compare, channel 1
11 ST Sleep Timer (not in Sleep Timer compare
CC2540/41)
RADIO1 Radio (CC2541) Radio DMA trigger 1 (see Section 25.3.2)
12 IOC_0 I/O controller Port 0 I/O pin input transition
(1)
13 IOC_1 I/O controller Port 1 I/O pin input transition
(1)
(1)
Using this trigger source must be aligned with port interrupt-enable bits. Note that all interrupt-enabled port pins generate a
trigger.
101
SWRU191CApril 2009Revised January 2012 DMA Controller
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Copyright © 20092012, Texas Instruments Incorporated

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Texas Instruments CC2541 Specifications

General IconGeneral
BrandTexas Instruments
ModelCC2541
CategoryMicrocontrollers
LanguageEnglish

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