Registers
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BSP_D0 (0x61E4) – CRC Value Byte 0
Bit
Name Reset R/W Description
No.
7:0
D[7:0]
0x00 R/W Bits 7:0 of d register in CRC sub-module
BSP_D1 (0x61E5) – CRC Value Byte 1
Bit
Name Reset R/W Description
No.
7:0
D[15:8]
0x5B R/W Bits 15:8 of d register in CRC sub-module
BSP_D2 (0x61E6) – CRC Value Byte 2
Bit
Name Reset R/W Description
No.
7:0
D[23:16]
0x06 R/W Bits 23:16 of d register in CRC sub-module
BSP_D3 (0x61E7) – CRC Value Byte 3
Bit
Name Reset R/W Description
No.
7:0
D[31:24]
0x00 R/W Bits 31:24 of d register in CRC sub-module
BSP_W (0x61E8) – Whitener Value
Bit
Name Reset R/W Description
No.
7
W_PN9_RESET
0 R0 When a 1 is written to this bit, the CC2500-compatible whitener is reset,
and all bits in the s and b registers are set to 1.
6:0
W[6:0]
110 R/W
Write: Writes all whitening registers. w
6
is set to BSP_W[0], w
5
is set to
0101
BSP_W[1] and so on up to w
1
is set to BSP_W[5]. w
0
is set to 1.
Read: Reads back w register. BSP_W[0] is set to w
6
, BSP_W[1] is
set to w
5
and so on up to BSP_W[6] is set to w
0
.
BSP_MODE (0x61E9) – Bit Stream Processor Configuration
Bit
Name Reset R/W Description
No.
7 – 0 R0 Reserved. Read as zero
6
CP_BUSY
0 R Coprocessor mode busy. Goes to 1 after a byte has been written to
BSP_DATA. Goes to 0 when a byte is ready to be read back from
BSP_DATA
5
CP_READOUT
0 R/W Coprocessor mode readout
4
CP_END
0 R/W Endianness of data in coprosessor mode.
0: LSB processed first
1: MSB processed first
3:2
CP_MODE[1:0]
00 R/W Coprocessor mode
00: Coprocessor disabled
01: Coprocessor receive mode
10: Reserved
11: Coprocessor transmit mode
1
W_PN9_EN
0 R/W Enable CC2500-compatible PN9 whitener
0
W_PN7_EN
1 R/W Enable PN7 whitener
BSP_DATA (0x61EA) – Bit Stream Processor Coprocessor Data
Bit
Name Reset R/W Description
No.
7:0
BSP_DATA[7:0]
0x00 R/W
When BSP_MODE.CP_BUSY = 0:
Write: Provide byte to be processed in coprocessor mode
Read: Read processed byte
352
CC2541 Proprietary Mode Radio SWRU191C– April 2009–Revised January 2012
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