Unused I/O Pins
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7.1 Unused I/O Pins
Unused I/O pins should have a defined level and not be left floating. One way to do this is to leave the pin
unconnected and configure the pin as a general-purpose I/O input with pullup resistor. This is also the
state of all pins during and after reset (except P1.0 and P1.1, which do not have pullup/pulldown
capability). Alternatively, the pin can be configured as a general-purpose I/O output. In either case, the pin
should not be connected directly to VDD or GND, in order to avoid excessive power consumption.
7.2 Low I/O Supply Voltage
In applications where the digital I/O power supply voltage pins, DVDD1 and DVDD2, are below 2.6 V, the
register bit PICTL.PADSC should be set to 1 in order to obtain the output dc characteristics specified in
the DC Characteristics table in the device data sheet (Appendix C).
7.3 General-Purpose I/O
When used as general-purpose I/O, the pins are organized as three 8-bit ports, Port 0, Port 1, and Port 2;
denoted P0, P1, and P2. P0 and P1 are complete 8-bit-wide ports, whereas P2 has only five usable bits.
All ports are both bit- and byte-addressable through the SFR registers P0, P1, and P2. Each port pin can
individually be set to operate as a general-purpose I/O or as a peripheral I/O.
The output drive strength is 4 mA on all outputs, except for the two high-drive outputs, P1.0 and P1.1,
which each have 20-mA output drive strength.
The registers PxSEL, where x is the port number 0–2, are used to configure each pin in a port as either a
general-purpose I/O pin or as a peripheral I/O signal. By default, after a reset, all digital input/output pins
are configured as general-purpose input pins.
To change the direction of a port pin, the registers PxDIR are used to set each port pin to be either an
input or an output. Thus, by setting the appropriate bit within PxDIR to 1, the corresponding pin becomes
an output.
When reading the port registers P0, P1, and P2, the logic values on the input pins are returned regardless
of the pin configuration. This does not apply during the execution of read-modify-write instructions. The
read-modify-write instructions are: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ, MOV, CLR, and SETB.
Operating on a port register, the following is true: When the destination is an individual bit in port register
P0, P1, or P2, the value of the register, not the value on the pin, is read, modified, and written back to the
port register.
When used as an input, the general-purpose I/O port pins can be configured to have a pullup, pulldown or
three-state mode of operation. By default, after a reset, inputs are configured as inputs with pullup. To
deselect the pullup or pulldown function on an input, the appropriate bit within the PxINP must be set to 1.
The I/O port pins P1.0 and P1.1 do not have pullup/pulldown capability. Note that pins configured as
peripheral I/O signals do not have pullup/pulldown capability, even if the peripheral function is an input.
In power modes PM1, PM2, and PM3, the I/O pins retain the I/O mode and output value (if applicable) that
was set when PM1/PM2/PM3 was entered.
7.4 General-Purpose I/O Interrupts
General-purpose I/O pins configured as inputs can be used to generate interrupts. The interrupts can be
configured to trigger on either a rising or falling edge of the external signal. Each of the P0, P1, and P2
ports has port interrupt-enable bits common for all bits within the port located in the IEN1–IEN2 registers
as follows:
• IEN1.P0IE: P0 interrupt enable
• IEN2.P1IE: P1 interrupt enable
• IEN2.P2IE: P2 interrupt enable
In addition to these common interrupt enables, the bits within each port have individual interrupt enables
located in SFR registers P0IEN, P1IEN, and P2IEN. Even I/O pins configured as peripheral I/O or
general-purpose outputs have interupts generated when enabled.
82
I/O Ports SWRU191C–April 2009–Revised January 2012
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