USB Registers
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USBCIE (0x620B) – Common USB Interrupt-Enable Mask
Bit Name Reset R/W Description
7:4 – R0 Reserved
3
SOFIE
0 R/W Start-of-frame interrupt enable
0: Interrupt disbled
1: Interrupt enabled
2
RSTIE
1 R/W Reset interrupt enable
0: Interrupt disbled
1: Interrupt enabled
1
RESUMEIE
1 R/W Resume interrupt enable
0: Interrupt disbled
1: Interrupt enabled
0
SUSPENDIE
0 R/W Suspend interrupt enable
0: Interrupt disbled
1: Interrupt enabled
USBFRML (0x620C) – Current Frame Number (Low Byte)
Bit Name Reset R/W Description
7:0
FRAME[7:0]
0x00 R Low byte of 11-bit frame number
USBFRMH (0x620D) – Current Frame Number (High Byte)
Bit Name Reset R/W Description
7:3 – – R0 Reserved
2:0
FRAME[10:8]
000 R 3 MSBs of 11-bit frame number
USBINDEX (0x620E) – Current-Endpoint Index Register
Bit Name Reset R/W Description
7:4 – – R0 Reserved
3:0
USBINDEX[3:0]
0000 R/W Endpoint selected. Must be set to a value in the range 0–5
USBCTRL (0x620F) – USB Control Register
Bit Name Reset R/W Description
7
PLL_LOCKED
0 R PLL locked status
6:3 – – R0 Reserved
2 – 0 R/W Reserved. Always write 0
1
PLL_EN
0 R/W 48-MHz USB PLL enable. When this bit is set, the 48-MHz PLL is started. However, the USB
must not be accessed before the PLL has locked, i.e. ,PLL_LOCKED is 1. This bit can only be set
when USB_EN = 1.
Note: The PLL must be disabled before exiting active mode and re-enabled after entering active
mode.
0
USB_EN
0 R/W USB enable. The USB controller is reset when writing 0 to this bit.
USBMAXI (0x6210) – Max. Packet Size for IN Endpoint{1–5}
Bit Name Reset R/W Description
7:0
USBMAXI[7:0]
0x00 R/W
Maximum packet size, in units of 8 bytes, for IN endpoint selected by USBINDEX register. The
value of this register should correspond to the wMaxPacketSize field in the standard endpoint
descriptor for the endpoint. This register must not be set to a value greater than the available
FIFO memory for the endpoint.
202
USB Controller SWRU191C– April 2009– Revised January 2012
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