Timer Tick Generation
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CLKCONSTA (0x9E) – Clock Control Status
Bit Name Reset R/W Description
7
OSC32K
1 R Current 32-kHz clock source selected:
0: 32-kHz XOSC
1: 32-kHz RCOSC
6
OSC
1 R Current system clock selected:
0: 32-MHz XOSC
1: 16-MHz RCOSC
5:3
TICKSPD[2:0]
001 R Current timer ticks output setting
000: 32 MHz
001: 16 MHz
010: 8 MHz
011: 4 MHz
100: 2 MHz
101: 1 MHz
110: 500 kHz
111: 250 kHz
2:0
CLKSPD
001 R Current clock speed
000: 32 MHz
001: 16 MHz
010: 8 MHz
011: 4 MHz
100: 2 MHz
101: 1 MHz
110: 500 kHz
111: 250 kHz
4.5 Timer Tick Generation
The value of the CLKCONCMD.TICKSPD register controls a global prescaler for Timer 1, Timer 3, and
Timer 4. The prescaler value can be set to a value from 0.25 MHz to 32 MHz. It should be noted that if
CLKCONCMD.TICKSPD indicates a higher frequency than the system clock, the actual prescaler value
indicated in CLKCONSTA.TICKSPD is the same as the system clock.
4.6 Data Retention
In power modes PM2 and PM3, power is removed from most of the internal circuitry. However, SRAM
retains its contents, and the content of internal registers is also retained in PM2 and PM3.
All CPU, RF, and peripheral registers retain their contents in PM2 and PM3, except the AES, I
2
C, and
USB registers, OBSSEL0–OBSSEL5, TR0, and in the CC2541, LLECTRL.
Switching to the PM2 or PM3 low-power modes appears transparent to software. Note that the value of
the Sleep Timer is not preserved in PM3.
All registers retain their values in PM1.
72
Power Management and Clocks SWRU191C– April 2009– Revised January 2012
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