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Memory
Table 2-1. SFR Overview (continued)
Register SFR
Module Description
Name Address
P1DIR 0xFE IOC Port 1 direction
P2DIR 0xFF IOC Port 2 direction
PMUX 0xAE IOC Power-down signal mux
MPAGE 0x93 MEMORY Memory page select
MEMCTR 0xC7 MEMORY Memory system control
FMAP 0x9F MEMORY Flash-memory bank mapping
RFIRQF1 0x91 RF RF interrupt flags MSB
RFD 0xD9 RF RF data
RFST 0xE1 RF RF command strobe
RFIRQF0 0xE9 RF RF interrupt flags LSB
RFERRF 0xBF RF RF error interrupt flags
ST0 0x95 ST Sleep Timer 0
ST1 0x96 ST Sleep Timer 1
ST2 0x97 ST Sleep Timer 2
STLOAD 0xAD ST Sleep-timer load status
SLEEPCMD 0xBE PMC Sleep-mode control command
SLEEPSTA 0x9D PMC Sleep-mode control status
CLKCONCMD 0xC6 PMC Clock control command
CLKCONSTA 0x9E PMC Clock control status
T1CC0L 0xDA Timer 1 Timer 1 channel 0 capture/compare value low
T1CC0H 0xDB Timer 1 Timer 1 channel 0 capture/compare value high
T1CC1L 0xDC Timer 1 Timer 1 channel 1 capture/compare value low
T1CC1H 0xDD Timer 1 Timer 1 channel 1 capture/compare value high
T1CC2L 0xDE Timer 1 Timer 1 channel 2 capture/compare value low
T1CC2H 0xDF Timer 1 Timer 1 channel 2 capture/compare value high
T1CNTL 0xE2 Timer 1 Timer 1 counter low
T1CNTH 0xE3 Timer 1 Timer 1 counter high
T1CTL 0xE4 Timer 1 Timer 1 control and status
T1CCTL0 0xE5 Timer 1 Timer 1 channel 0 capture/compare control
T1CCTL1 0xE6 Timer 1 Timer 1 channel 1 capture/compare control
T1CCTL2 0xE7 Timer 1 Timer 1 channel 2 capture/compare control
T1STAT 0xAF Timer 1 Timer 1 status
T2CTRL 0x94 Timer 2 Timer 2 control
T2EVTCFG 0x9C Timer 2 Timer 2 event configuration
T2IRQF 0xA1 Timer 2 Timer 2 interrupt flags
T2M0 0xA2 Timer 2 Timer 2 multiplexed register 0
T2M1 0xA3 Timer 2 Timer 2 multiplexed register 1
T2MOVF0 0xA4 Timer 2 Timer 2 multiplexed overflow register 0
T2MOVF1 0xA5 Timer 2 Timer 2 multiplexed overflow register 1
T2MOVF2 0xA6 Timer 2 Timer 2 multiplexed overflow register 2
T2IRQM 0xA7 Timer 2 Timer 2 interrupt mask
T2MSEL 0xC3 Timer 2 Timer 2 multiplex select
T3CNT 0xCA Timer 3 Timer 3 counter
T3CTL 0xCB Timer 3 Timer 3 control
T3CCTL0 0xCC Timer 3 Timer 3 channel 0 compare control
T3CC0 0xCD Timer 3 Timer 3 channel 0 compare value
T3CCTL1 0xCE Timer 3 Timer 3 channel 1 compare control
33
SWRU191C–April 2009–Revised January 2012 8051 CPU
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