Debug Interface
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7.6.6 ADC
In Table 7-1, the ADC signals are shown as follows:
• A0: ADC input 0
• A1: ADC input 1
• A2: ADC input 2
• A3: ADC input 3
• A4: ADC input 4
• A5: ADC input 5
• A6: ADC input 6
• A7: ADC input 7
• T: ADC external trigger pin
When using the ADC, Port 0 pins must be configured as ADC inputs. Up to eight ADC inputs can be used.
To configure a Port 0 pin to be used as an ADC input, the corresponding bit in the APCFG register must be
set to 1. The default values in this register select the Port 0 pins as non-ADC input, i.e., digital
input/outputs.
The settings in the APCFG register override the settings in P0SEL.
The ADC can be configured to use the general-purpose I/O pin P2.0 as an external trigger to start
conversions. P2.0 must be configured as a general-purpose I/O in input mode when being used for ADC
external trigger.
7.6.7 Operational Amplifier and Analog Comparator
When using the operational amplifier and analog comparator, the corresponding Port 0 pins must be
configured as ADC inputs (see Table 7-1). To configure a Port 0 pin to be used as an ADC input, the
corresponding bit in the APCFG register must be set to 1. The default values in this register select the Port
0 pins as non-ADC input, i.e., digital input/outputs.
The settings in the APCFG register override the settings in P0SEL.
7.7 Debug Interface
Ports P2.1 and P2.2 are used for debug data and clock signals, respectively. These are shown as DD
(debug data) and DC (debug clock) in Table 7-1. When in debug mode, the debug interface controls the
direction of these pins. Pullup/pulldown is disabled on these pins while in debug mode.
7.8 32-kHz XOSC Input
Ports P2.3 and P2.4 can be used to connect an external 32-kHz crystal. These port pins are used by the
32-kHz XOSC when CLKCONCMD.OSC32K is low, regardless of register settings. The port pins are set in
analog mode when CLKCONCMD.OSC32K is low.
7.9 Radio Test Output Signals
By using the OBSSELx registers (OBSSEL0–OBSSEL5) the user can output different signals from the RF
Core to GPIO pins. These signals can be useful for debugging of low-level protocols or control of external
PA, LNA, or switches. The control registers OBSSEL0–OBSSEL5 can be used to override the standard
GPIO behavior and output RF Core signals (rfc_obs_sig0, rfc_obs_sig1, and rfc_obs_sig2) on
the pins P1[0:5]. For a list of available signals, see the respective RFC_OBS_CTRLx registers in
Section 23.15.3 for CC253x or Section 24.1 for CC2540 or Chapter 25 for CC2541.
7.10 Power-Down Signal MUX (PMUX)
The PMUX register can be used to output the 32-kHz clock and/or the digital regulator status.
86
I/O Ports SWRU191C–April 2009–Revised January 2012
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