TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T –APRIL 2001–REVISED MAY 2012
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● If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1,
READYMODE = 1), then:
1. Lead: LR ≥ t
c(XTIM)
LW ≥ t
c(XTIM)
2. Active: AR ≥ 2 × t
c(XTIM)
AW ≥ 2 × t
c(XTIM)
NOTE: Restriction does not include external hardware wait states
3. Lead + Active: LR + AR ≥ 4 × t
c(XTIM)
LW + AW ≥ 4 × t
c(XTIM)
NOTE: Restriction does not include external hardware wait states
These requirements result in the following XTIMING register configuration restrictions (no hardware to
detect illegal XTIMING configurations):
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
≥ 1 ≥ 2 0 ≥ 1 ≥ 2 0 0, 1
or (no hardware to detect illegal XTIMING configurations):
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
≥ 2 ≥ 1 0 ≥ 2 ≥ 1 0 0, 1
Examples of valid and invalid timing when using asynchronous XREADY (no hardware to detect illegal
XTIMING configurations):
XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING
Invalid 0 0 0 0 0 0 0, 1
Invalid 1 0 0 1 0 0 0, 1
Invalid 1 1 0 1 1 0 0
Valid 1 1 0 1 1 0 1
Valid 1 2 0 1 2 0 0, 1
Valid 2 1 0 2 1 0 0, 1
128 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated
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