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TMS570LS0714
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SPNS226E –JUNE 2013–REVISED NOVEMBER 2016
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System Information and Electrical SpecificationsCopyright © 2013–2016, Texas Instruments Incorporated
Table 6-13. Clock Domain Descriptions (continued)
CLOCK
DOMAIN
DEFAULT
SOURCE
SOURCE
SELECTION
REGISTER
SPECIAL CONSIDERATIONS
VCLKA1 VCLK VCLKASRC
• Defaults to VCLK as the source
• Is disabled through the CDDISx registers bit 4
RTICLK VCLK RCLKSRC
• Defaults to VCLK as the source
• If a clock source other than VCLK is selected
for RTICLK, then the RTICLK frequency must
be less than or equal to VCLK/3
– Application can ensure this by
programming the RTI1DIV field of the
RCLKSRC register, if necessary
• Is disabled through the CDDISx registers bit 6
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