Xilinx Spartan-6 FPGA Series User Manual

34 www.xilinx.com Spartan-6 FPGA PCB Design and Pin Planning
UG393 (v1.1) April 29, 2010
Chapter 2: Power Distribution System
Figure 2-9 shows an averaged noise measurement taken at the V
CCO
pins of a sample
design. In this case, the trigger was the clock for an I/O bus interface sending a 1-0-1-0
pattern at 250 Mb/s.
X-Ref Target - Figure 2-9
Figure 2-9: Averaged Measurement of V
CCO
Supply with Multiple I/O Sending
Patterns at 250 Mb/s
ug393_c2_09_091809

Xilinx Spartan-6 FPGA Series Specifications

General

Device Family	Spartan-6
Category	FPGA
Number of Logic Cells	3, 840 to 147, 443
Block RAM	216 Kb to 4, 824 Kb
Maximum User I/O	102 to 576
Process Technology	45nm
Operating Voltage	1.2V
Number of DSP Slices	8 to 180
Package Options	FG256, FG484, FG676, FG900, FG1156, FT256, FTG256, FTG484, FTG676, FTG900, FTG1156