Xinje XD5 - Page 120

119
Two operands
D
Be subtracted data and result address
16 bits /32 bits,BIN
S1
Subtract data address
16 bits /32 bits,BIN
Suitable soft component
*Notes: D includes D, HD; TD includes TD, HTD; CD includes CD, HCD, HSCD, HSD;
DM includes DM, DHM; DS includes DS, DHS.
<Three operands>
SUB D10 D12 D14
X0
S1· S2· D·
appoint the soft unit’s content, subtract the soft unit’s content appointed by in the
format of algebra. The result will be stored in the soft unit appointed by (5-(-8)=13).
The action of each flag, the setting method of 32 bits operation’s soft units are both the same
with the preceding ADD instruction.
The importance is: in the preceding program, if X0 is ON, SUB operation will be executed
every scan cycle.
Refer to chapter 4-6-1 for flag action and functions.
<Two operands>
SUB D10 D12
X0
S1·D·
appoint the soft unit’s content, subtract the soft unit’s content appointed by in the
format of algebra. The result will be stored in the soft unit appointed by (5-(-8)=13)
The action of each flag, the setting method of 32 bits operation’s soft units are both the same
with the preceding ADD instruction.
The importance is: in the preceding program, if X0 is ON, SUB operation will be executed
every scan cycle. Rising or falling pulse edge is recommended to activate the instruction.
Refer to chapter 4-6-1 for flag action and functions.
Operand
System
Constant
Module
D
*
FD
TD
*
CD
*
DX
DY
DM
*
DS
*
K /H
ID
QD
Three operands
S1
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S2
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D
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Two operands
D
●
S1
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Word
(D10) — (D12) → (D14)
Description
S1·
S2·
D·
(D10) — (D12) → (D10)
S1·
S2·
D·