Xinje XD5 - AB Phase 100-Segment HSC [CNT_AB]

197
on state.
5-9-3．AB phase 100-segment HSC [CNT_AB]
Summarization
AB phase 100-segment HSC instruction.
AB phase 100-segment HSC [CNT_AB]
16 bits instruction
-
32 bits instruction
CNT_AB
Execution condition
Normal ON/OFF
Suitable model
XD, XL (exclude
XL1, XD1)
Hardware
requirements
-
Software
requirements
-
Operand
Operand
Function
Type
S1
Set the HSC (such as:HSC0)
32 bits, BIN
S2
Set the compare value (such as: K100, D0 )
32 bits, BIN
S3
Set the 100-segment setting value
32 bits, BIN
Suitable soft components
*Notes: D includes D, HD; TD includes TD, HTD; CD includes CD, HCD, HSCD, HSD;
DM includes DM, DHM; DS includes DS, DHS.
CNT_AB HSC0 HD0
S1.
S2.
M0
HD100
S3.
 When the high-speed counter HSC0 counts in AB phase mode, high-speed counting
value is compared to data block starting from HD100 (such as HD102, HD102, HD104
and other double-word registers), it will immediately produce the corresponding high-
speed counting interrupt when the condition is met, each section of the corresponding
interrupt marks please refer to chapter 5-9-4.
 During the high-speed counting process, it is invalid to modify the set value of 100
segments.
 In the process of high-speed counting, the driving condition M0 can not be
disconnected. If M0 is disconnected and then rebooted, no interruption will occur. The
high-speed counter must be reset first, and then set ON M0 again to produce
interruption.
Description
Operand
System
Constant
Module
D
*
FD
TD
*
CD
*
DX
DY
DM
DS
*
K /H
ID
QD
S1
Only can be HSC
S2
●
●
S3
●
Word