Xinje XD5 - Logic Converse [CML]

127
4-6-8．Logic converse [CML]
1. Summary
Logic converse the data
Converse [CML]
16 bits
CML
32 bits
DCML
Execution
condition
Normally ON/OFF,
rising/falling edge
Suitable
Models
XD, XL
Hardware
requirement
-
Software
requirement
-
2. Operands
Operands
Function
Data Type
S
Source data address
16 bits/32 bits, BIN
D
Result address
16 bits/32 bits, BIN
3. Suitable soft components
*Notes: D includes D, HD; TD includes TD, HTD; CD includes CD, HCD, HSCD, HSD;
DM includes DM, DHM; DS includes DS, DHS.
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
D0
Y17 Y7 Y6 Y5 Y4
Sign
bit
（0=positive，
1=negative）
Each data bit in the source device is reversed (1→0, 0→1) and sent to the destination device.
If use constant K in the source device, it can be auto convert to be binary.
This instruction is fit for PLC logical converse output.
< Read the converse input >
CML D0 DY0
S· D·
M0
↑
Word
Operand
System
Constant
Module
D
*
FD
TD
*
CD
*
DX
DY
DM
*
DS
*
K /H
ID
QD
S
●
●
●
●
●
●
●
●
●
D
●
●
●
●
●
●
Description