Xinje XD5 - Page 123

122
3. Suitable soft components
*Notes: D includes D, HD; TD includes TD, HTD; CD includes CD, HCD, HSCD, HSD;
DM includes DM, DHM; DS includes DS, DHS.
<16 bits operation >
DIV D0 D2 D4
X0
S1· S2· D·
appoints the dividend soft component, appoints the divisor soft component,
and the next address appoint the soft component of the result and the remainder.
In the above example, if input X0 is ON, devision operation is executed every scan cycle.
<32 bits operation >
DDIV D0 D2 D4
X1
S1· S2· D·
The dividend is composed by the device appointed by and the next one. The divisor is
composed by the device appointed by and the next one. The result and the remainder are
stored in the four sequential devices, the first one is appointed by
If the value of the divisor is 0, the instruction will be error.
The highest bit of the result and remainder is the symbol bit (positive:0, negative: 1). When
any of the dividend or the divisor is negative, then the result will be negative. When the
dividend is negative, then the remainder will be negative.
Operand
System
Constant
Module
D
*
FD
TD
*
CD
*
DX
DY
DM
*
DS
*
K /H
ID
QD
S1
●
●
●
●
●
●
●
●
●
S2
●
●
●
●
●
●
●
●
●
D
●
●
●
●
●
●
Word
Dividend Divisor Result Remainder
BIN BIN BIN BIN
(D0) ÷ (D2) → (D4) ┅ (D5)
16 bits 16 bits 16 bits 16 bits
Description
D·
S2·
S1·
Dividend Divisor Result Remainder
BIN BIN BIN BIN
(D1, D0) ÷ (D3, D2) (D5, D4) ┅ (D7, D6)
32 bits 32 bits 32 bits 32 bits
S1·
S2·
D·