Xinje XD5 - Page 176

175
2. operand
Operand
Function
Model
S1
The first clock soft component address
16 bits, BIN
S2
The second clock soft component address
16 bits, BIN
S3
The third clock soft component address
16 bits, BIN
S4
PLC real time clock information first address
16 bits, BIN
D2
The compare result first address
bit
3. suitable soft component
*Notes: D includes D, HD; TD includes TD, HTD; CD includes CD, HCD, HSCD, HSD;
DM includes DM, DHM; DS includes DS, DHS.
M includes M, HM, SM; S includes S, HS; T includes T, HT; C includes C, HC.
TCMP D20 D21 D22
M0
X0
D·
S1·
S2·
S3·
D20
M0
M1
M2
D30
TRD D30
S4·
D22D21
D30
D32D31
D20 D22D21
D30 D32D31
D20
D22D21
D30
D32D31
=
<
>
TRD will read the present clock information in D30~D36 (year, month, day, hour, minute,
second, week).
X0 from OFF to ON, TCMP worked. Compare the three registers starting from S4 to three
registers S1, S2, S3 (year, month, day). When S1, S2, S3 is larger than S4 clock, M0 is ON.
When S1, S2, S3 is equal to S4 clock, M1 is ON. When S1, S2, S3 is smaller than S4 clock,
M2 is ON.
Operand
System
Constant
Module
D
*
FD
TD
*
CD
*
DX
DY
DM
*
DS
*
K /H
ID
QD
S1
●
●
●
●
●
●
●
S2
●
●
●
●
●
●
●
S3
●
●
●
●
●
●
●
S4
●
●
●
●
●
●
●
Word
Operand
System
X
Y
M
*
S
*
T
*
C
*
Dn.m
D
●
●
●
Bit
Description
Even X0=OFF to stop instruction TCMP, M0~M2 still keep the
state before X0 become OFF.