YOKOGAWA EML500 Series - Appendix 4: Speed Indicator Block Diagram

A-4
IM80B80T10E 21th Edition : Jul.1,2007-00
< Appendix >
Appendix 4: Speed Indicator Block Diagram
1 2 3 4 5 6 7 8 9
10
VCC
GND
+V
COM
DC . DC
CONV
+24V → VCC
POWER SUPPLY
PROCESSOR
I/O DECORDER
MPU
INT
CTC
PIO SIO
ROM RAM
Real Time INTRATE CLR
PA7 PA0 PB7 PB0
A15
A0
D7 D0
TxD
RxD
32k
(128k)
128k
(effective:
32k )
PIO CH A PIO CH B
DATA BUS
ADRS BUS
+24V
GND
FG
RD A
RDB
TD A
TD B
SHLD
1 2 3 4 5 6 7 8 9
10
DATA BUS D7 ~ D0
CONTROL SIGNAL
MOTOR DRIVER
STEP MOTOR #1
(zero detection)
(minimum− point detection)
(maximum− point detection)
STEP MOTOR #2
(zero detection)
(minimum− point detection)
(maximum− point detection)
MOTOR
CONTROLLER #1
MOTOR DRIVER #1
MOTOR
CONTROLLER #2
MOTOR DRIVER #2
Note: The #2 system is optional.
TD A/B : not used.