MC96F6432
June 22, 2018 Ver. 2.9 11
Table 7-1 Absolute Maximum Ratings .................................................................................................... 36
Table 7-2 Recommended Operating Conditions ..................................................................................... 36
Table 7-3 A/D Converter Characteristics ................................................................................................ 37
Table 7-4 Power-on Reset Characteristics ............................................................................................. 37
Table 7-5 LVR and LVI Characteristics ................................................................................................... 38
Table 7-6 High Internal RC Oscillator Characteristics ............................................................................. 39
Table 7-7 Internal WDTRC Oscillator Characteristics ............................................................................. 39
Table 7-8 LCD Voltage Characteristics ................................................................................................... 40
Table 7-9 DC Characteristics .................................................................................................................. 41
Table 7-10 AC Characteristics ................................................................................................................ 43
Table 7-11 SPI0/1/2 Characteristics ....................................................................................................... 44
Table 7-12 UART0/1 Characteristics ...................................................................................................... 45
Table 7-13 I2C0/1 Characteristics .......................................................................................................... 46
Table 7-14 Data Retention Voltage in Stop Mode ................................................................................... 47
Table 7-15 Internal Flash Rom Characteristics ....................................................................................... 48
Table 7-16 Input/Output Capacitance ..................................................................................................... 48
Table 7-17 Main Clock Oscillator Characteristics ................................................................................... 49
Table 7-18 Sub Clock Oscillator Characteristics ..................................................................................... 50
Table 7-19 Main Oscillation Stabilization Characteristics........................................................................ 51
Table 7-20 Sub Oscillation Stabilization Characteristics ......................................................................... 51
Table 8-1 SFR Map Summary ................................................................................................................ 63
Table 8-2 SFR Map Summary ................................................................................................................ 64
Table 8-3 SFR Map................................................................................................................................. 65
Table 9-1 Port Register Map ................................................................................................................... 73
Table 10-1 Interrupt Group Priority Level ................................................................................................ 93
Table 10-2 Interrupt Vector Address Table ............................................................................................. 96
Table 10-3 Interrupt Register Map ........................................................................................................ 103
Table 11-1 Clock Generator Register Map ........................................................................................... 111
Table 11-2 Basic Interval Timer Register Map ...................................................................................... 114
Table 11-3 Watch Dog Timer Register Map .......................................................................................... 117
Table 11-4 Watch Timer Register Map ................................................................................................. 120
Table 11-5 Timer 0 Operating Modes ................................................................................................... 122
Table 11-6 Timer 0 Register Map ......................................................................................................... 129
Table 11-7 Timer 1 Operating Modes ................................................................................................... 131
Table 11-8 Timer 2 Register Map ......................................................................................................... 137
Table 11-9 Timer 2 Operating Modes ................................................................................................... 141
Table 11-10 Timer 3 Register Map ....................................................................................................... 148
Table 11-11 Timer 3, 4 Operating Modes ............................................................................................. 152
Table 11-12 PWM Frequency vs. Resolution at 8 MHz ........................................................................ 158
Table 11-13 PWM Channel Polarity ...................................................................................................... 158
Table 11-14 Timer 3, 4 Register Map ................................................................................................... 170
Table 11-15 Buzzer Frequency at 8 MHz ............................................................................................. 181
Table 11-16 Buzzer Driver Register Map .............................................................................................. 182
Table 11-17 SPI 2 Register Map ........................................................................................................... 186
Table 11-18 ADC Register Map ............................................................................................................ 192
Table 11-19 Equations for Calculating USI0 Baud Rate Register Setting ............................................. 198
Table 11-20 CPOL0 Functionality ......................................................................................................... 206
Table 11-21 USI0 Register Map ........................................................................................................... 223
Table 11-22 Equations for Calculating USI1 Baud Rate Register Setting ............................................. 235