MC96F6432
June 22, 2018 Ver. 2.9 199
11.12.5 USI0 External Clock (SCK0)
External clocking is used in the synchronous mode of operation.
External clock input from the SCK0 pin is sampled by a synchronization logic to remove meta-stability. The
output from the synchronization logic must be passed through an edge detector before it is used by the
transmitter and receiver. This process introduces two CPU clock period delay. The maximum frequency of the
external SCK0 pin is limited up-to 1MHz.
11.12.6 USI0 Synchronous mode operation
When synchronous or SPI mode is used, the SCK0 pin will be used as either clock input (slave) or clock output
(master). Data sampling and transmitter is issued on the different edge of SCK0 clock each other. For example, if
data input on RXD0 (MISO0 in SPI mode) pin is sampled on the rising edge of SCK0 clock, data output on TXD0
(MOSI0 in SPI mode) pin is altered on the falling edge.
The CPOL0 bit in USI0CR1 register selects which SCK0 clock edge is used for data sampling and which is used
for data change. As shown in the figure below, when CPOL0 is zero, the data will be changed at rising SCK0
edge and sampled at falling SCK0 edge.
Figure 11.59 Synchronous Mode SCK0 Timing (USI0)
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