MC96F6432
June 22, 2018 Ver. 2.9 207
Figure 11.64 USI0 SPI Clock Formats when CPHA0=0
When CPHA0=0, the slave begins to drive its MISO0 output with the first data bit value when SS0 goes to active
low. The first SCK0 edge causes both the master and the slave to sample the data bit value on their MISO0 and
MOSI0 inputs, respectively. At the second SCK0 edge, the USI0 shifts the second data bit value out to the
MOSI0 and MISO0 outputs of the master and slave, respectively. Unlike the case of CPHA0=1, when CPHA0=0,
the slave’s SS0 input must go to its inactive high level between transfers. This is because the slave can prepare
the first data bit when it detects falling edge of SS0 input.
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