Abov MC96F6432 Series - 11.2.3 Register Map; 11.2.4 Basic Interval Timer Register Description; 11.2.5 Register Description for Basic Interval Timer

MC96F6432
114 June 22, 2018 Ver. 2.9
11.2.3 Register Map
Table 11-2 Basic Interval Timer Register Map
Name
Address
Dir
Default
Description
BITCNT
8CH
R
00H
Basic Interval Timer Counter Register
BITCR
8BH
R/W
01H
Basic Interval Timer Control Register
11.2.4 Basic Interval Timer Register Description
The basic interval timer register consists of basic interval timer counter register (BITCNT) and basic interval
timer control register (BITCR). If BCLR bit is set to ‘1’, BITCNT becomes ‘0’ and then counts up. After 1 machine
cycle, BCLR bit is cleared to ‘0’ automatically.
11.2.5 Register Description for Basic Interval Timer
BITCNT (Basic Interval Timer Counter Register) : 8CH
7
6
5
4
3
2
1
0
BITCNT7
BITCNT6
BITCNT5
BITCNT4
BITCNT3
BITCNT2
BITCNT1
BITCNT0
R
R
R
R
R
R
R
R
Initial value : 00H
BITCNT[7:0]
BIT Counter