Abov MC96F6432 Series User Manual

MC96F6432
June 22, 2018 Ver. 2.9 223
11.12.22 Register Map
Table 11-21 USI0 Register Map
Name
Address
Dir
Default
Description
USI0BD
E3H
R/W
FFH
USI0 Baud Rate Generation Register
USI0DR
E5H
R/W
00H
USI0 Data Register
USI0SDHR
E4H
R/W
01H
USI0 SDA Hold Time Register
USI0SCHR
E7H
R/W
3FH
USI0 SCL High Period Register
USI0SCLR
E6H
R/W
3FH
USI0 SCL Low Period Register
USI0SAR
DDH
R/W
00H
USI0 Slave Address Register
USI0CR1
D9H
R/W
00H
USI0 Control Register 1
USI0CR2
DAH
R/W
00H
USI0 Control Register 2
USI0CR3
DBH
R/W
00H
USI0 Control Register 3
USI0CR4
DCH
R/W
00H
USI0 Control Register 4
USI0ST1
E1H
R/W
80H
USI0 Status Register 1
USI0ST2
E2H
R
00H
USI0 Status Register 2
11.12.23 USI0 Register Description
USI0 module consists of USI0 baud rate generation register (USI0BD), USI0 data register (USI0DR), USI0 SDA
hold time register (USI0SDHR), USI0 SCL high period register (USI0SCHR), USI0 SCL low period Register
(USI0SCLR), USI0 slave address register (USI0SAR), USI0 control register 1/2/3/4 (USI0CR1/2/3/4), USI0
status register 1/2 (USI0ST1/2).
11.12.24 Register Description for USI0
USI0BD (USI0 Baud- Rate Generation Register: For UART and SPI mode) : E3H
7
6
5
4
3
2
1
0
USI0BD7
USI0BD 6
USI0BD 5
USI0BD 4
USI0BD 3
USI0BD 2
USI0BD 1
USI0BD 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : FFH
USI0BD[7:0]
The value in this register is used to generate internal baud rate in
asynchronous mode or to generate SCK0 clock in SPI mode. To
prevent malfunction, do not write ‘0’ in asynchronous mode and do
not write ‘0’ or ‘1’ in SPI mode.
NOTE) In common with USI0SAR register, USI0BD register is
used for slave address register when the USI0 I2C mode.

Abov MC96F6432 Series Specifications

General

Brand	Abov
Model	MC96F6432 Series
Category	Microcontrollers
Language	English