Abov MC96F6432 Series User Manual

MC96F6432
June 22, 2018 Ver. 2.9 197
11.12.3 USI0 UART Block Diagram
RXD0
Rx
Control
Clock
Recovery
Receive Shift Register
(RXSR)
Data
Recovery
DOR0/PE0/FE0
Checker
USI0DR[0], USI0RX8[0], (Rx)
USI0DR[1], USI0RX8[1], (Rx)
TXD0
Tx
Control
Stop bit
Generator
Parity
Generator
Transmit Shift Register
(TXSR)
USI0DR, USI0TX8, (Tx)
USI0P[1:0]
M
U
X
LOOPS0
TXC0
TXCIE0 DRIE0
DRE0
Empty signal
To interrupt
block
INT_ACK
Clear
RXC0
RXCIE0WAKEIE0
WAKE0
At Stop mode
To interrupt
block
SCLK
(fx: System clock)
Low level
detector
2
USI0S[2:0]
3
USI0S[2:0]
3
TXE0
RXE0
DBLS0
USI0SB
Baud Rate Generator
USI0BD
I
N
T
E
R
N
A
L
B
U
S
L
I
N
E
SCK0
ACK
Control
Clock
Sync Logic
Master
USI0MS[1:0]
M
U
X
M
U
X
USI0MS[1:0]
USI0MS[1:0]
2
2
2
Figure 11.57 USI0 UART Block Diagram

Abov MC96F6432 Series Specifications

General

Brand	Abov
Model	MC96F6432 Series
Category	Microcontrollers
Language	English