8719ET/8720ET OVERALL BLOCK DIAGRAM FOR STANDARD, OPT 004
8719ET/8720ET OVERALL BLOCK DIAGRAM FOR STANDARD, OPT 004
sb511e
SOURCE
A26 HIGH STABILITY
FREQUENCY REFERENCE
(OPTION 1D5)
10 MHz
10 MHz ADJ
A59 SOURCE INTERFACE
CONTROL
AND
BIAS
EXT
AM
LOW BAND ADJ
ALC
OFFSET
SLOPE
LO MED HI
BLANKING ADJ
SOURCE CONTROL SWITCHES FROM A9
LOWBAND
OSCILLATORS
M/A/D/S
A11 PHASE LOCK
10 MHz
PRECISION
REFERENCE
EXT
REF IN
JUMPER (ONLY USED WITH OPTION 1D5)
PLL FROM
SOURCE
CONTROL
BOARD
10
W2
1st IF 10 MHz
PL REF
1 MHz
PRETUNE
DAC
PRETUNE
FM YIG2
FM YIG1
RED LED
"UNLOCK"
RED LED
NORMAL= FLASHING
AMBER LED
"PULL DOWN"
A12 REFERENCE
MAIN YIG2
A55 YIG1
2.55-20 GHz
W7
A29
A20
W6
J3
W3
W42
0.05-2.55 GHz
LOWBAND
W11
3.8 GHz
A53
MIXER/
AMP
A57
FIXED
OSC
A58 M/A/D/S
J1
J3
J2
STEP
RECOVERY
DIODE
A52 PULSE
GENERATOR
A14 FRACTIONAL-N (DIGITAL)
4
4
N
VCO
60 TO 240 MHz
COUNTER
INPUTS
v
COUNT
GATE
(23)
A13 FRACTIONAL-N (ANALOG)
API ADJ
100 kHZ
FROM A12
API s
TO A10
LSWP
VCXO
40 MHz
10 MHz
1 MHz
4 MHz TO A10
100 kHz TO A13
16 kHz
VCXO ADJ
39.984 MHz
40 MHz
f(11) IF
v(12) IF DET
v(8)
SWPERR
+0.25/GHz
v (9)
f(17) PL REF
V(18)
f(14) 100kHz
v(15) VCO TUNE
VCXO
TUNE
W40
v(13)
EXT REF
VCO
f(16) 2nd LO 9.996 MHz
F=40 MHz
FN VCOTUNE
v(21)
CAUTION
1.5KV AC START UP
680V AC STEADY STATE
LEGEND
DIGITAL BUS
This indicates Analog Bus node location.
f = Frequency Node
v = Voltage Node
W88
W82
W81
W1
W31
W9
W8
POWER
A15 PREREGULATOR
A8 POST-REGULATOR
REGULATORS
SWITCHING
POWER
SUPPLY
AND
REGULATOR
A51 TEST SET
INTERFACE
CONTROL
AND
BIAS
STEP
ATTENUATORS
TRANSFER SWITCH
LOWER FT. PANEL
BIAS TO BIAS TEE'S
NORMAL= ON, STEADY
9 GREEN LEDS
NORMAL= OFF
NORMAL= ON
GREEN LED
RED LED
LINE
POWER
A15W1
FAN POWER
MICROCIRCUIT POWER
INSTRUMENT POWER
+25V
+18V
+8V
-8V
-18V
+5VD
A16 REAR PANEL
TEST SET-I/0
INTERFACE
TEST SET-I/0
INTERFACE
EXT BIAS
EXT REF
AUX INPUT
EXT TRIG
EXT AM
TEST SEQ
LIMIT TEST
MEAS RESTART
TO A17
TO A12
TO A10
TO A17
FROM A9
TO A17
A7 CPU
DIN KYBD
INTERCONNECT
RS-232
INTERCONNECT
PARALLEL
INTERCONNECT
GPIB
INTERCONNECT
A1 FRONT PANEL
MEASURE
RESTART
A21
KEYBOARD
RPG
FRONT
PANEL
PROCESSOR
A2 FRONT PANEL PROCESSOR
A3 DISK
DRIVE
A22 DISPLAY
INTERFACE
VGA
INTERFACE
VGA
INTERCONNECT
TO A9
TO A10
TO A51
TO A12
TO A11
TO A14
A19 GSP
DIGITAL
INTERFACE
VIDEO
PALETTE
MEMORY
A18 DISPLAY
TFT
LIQUID
CRYSTAL
DISPLAY
(LCD)
XXX
LIGHT
A20
INVERTER ASSY
+5 VD
FROM A17
MOTHERBOARD
MAIN RAM
CONTROL/REFRESH
W83
W99
W82
RECEIVER
A10 DIGITAL IF
TIMING
CONTROL
ADC
ANALOG
BUS
AUX IN
A17
MOTHERBOARD
S
S
1/2
4 MHz FROM A12
SAMPLE
RATE IS
16 kHz
A OUT
B OUT
R OUT
IFA 4 kHz
IFB 4 kHz
IFR 4 kHz
TP18
TP20
TP16
INSTRUMENT
NODES
LSWP (FROM A14)
EXT TRIG
A9 SOURCE CONTROL BOARD
S11
S12
TRL
CAL
S11
S21
S12
S22
REV
FWD
TRL
CAL
S21
S22
W23
W34
W21
SAMPLER
BIAS
A65 A SAMPLER
A66 B SAMPLER
F=30 MHz
F=30 MHz
F=30 MHz
J2
J1
J1
J1
A64 R1 SAMPLER
J3
J3
J3
v(1)
+0.37V
v(2)
+2.5V
v(4)
A10 GND
AUX
INPUT
v(3)
A4 2nd CONVERTER
A6 2nd CONVERTER
A5 2nd CONVERTER
SOURCE
CONTROL
SWITCHES TO
A59
W47
W48
W46
PLL OUT TO
PHASE LOCK BD.
W49
SIGNAL SEPARATION
A62 DIRECTIONAL
COUPLER
REFLECTION
TRANSMISSION
W74
DIN KYBD PORT
INTERFACE
RS-232 PORT
INTERFACE
PARALLEL PORT
INTERFACE
GPIB PORT
INTERFACE
DIGITAL SIGNAL
PROCESSOR
ROM RAM
ADC
REG
EEPROM
MAIN CPU
FLASH
RAM
A69 STEP ATTN
W32
W90
W76
STANDARD
OPTION 004
W78
A27 ATTN
J2
J2
MAIN YIG1
A68 6 dB
ATTN
A17
W72
A28 DC BLOCK
W30
S
SRC TUNE
SET DAC # LOWBAND
» 4000 READ > 8 dBm
SRC TUNE
SET DAC # HIGH & MIDBAND
3200-4095 READ > 0 dBm
SET DAC # LOWBAND
3750-4095 READ > -5 dBm
CW 1 GHz
TEST PORT POWER -5 dBm
OPEN ON TEST PORT
10 MHz SINEWAVE 0.1V p-p
SMB TEE: A4, A5 OR A6
SRC TUNE
SET DAC # TO 4000
FOR HIGH, MID, & LOWBAND
J2 READS > -5 dBm
J3 READ > -19 dBm
To Next Page
Loading...
Need help?
General
