System Basics Introduction
Page 216 7210 SAS M, T, X, R6 Basic System Configuration Guide
Figure 14: Conventional Network Timing Architecture (North American Nomenclature)
The architecture shown in Figure 14 provides the following benefits:
• Limits the need for high quality clocks at each network element and only requires that
they reliably replicate input to remain traceable to its reference.
• Uses reliable physical media to provide transport of the timing signal. It does not consume
any bandwidth and requires limited additional processing.
The synchronization network is designed so a clock always receives timing from a clock of equal
or higher stratum or quality level. This ensures that if an upstream clock has a fault condition (for
example, loses its reference and enters a holdover or free-run state) and begins to drift in
frequency, the downstream clock will be able to follow it. For greater reliability and robustness,
most offices and nodes have at least two synchronization references that can be selected in priority
order (such as primary and secondary).
Further levels of resiliency can be provided by designing a capability in the node clock that will
operate within prescribed network performance specifications without any reference for a
specified timeframe. A clock operating in this mode is said to hold the last known state over (or
holdover) until the reference lock is once again achieved. Each level in the timing hierarchy is
associated with minimum levels of network performance.
Each synchronization capable port can be independently configured to transmit data using the
node reference timing. In addition, some TDM channels can use adaptive timing or loop timing.
Transmission of a reference clock through a chain of Ethernet equipment requires that all
equipment supports Synchronous Ethernet. A single piece of equipment that is not capable of
performing Synchronous Ethernet breaks the chain. Ethernet frames will still get through but
downstream devices should not use the recovered line timing as it will not be traceable to an
acceptable stratum source.
Central Synchronization Sub-System
The timing subsystem for the platforms has a central clock located on the CPM. The timing
subsystem performs many of the duties of the network element clock as defined by Telcordia (GR-
1244-CORE) and ITU-T G.781.
The central clock uses the available timing inputs to train its local oscillator. The number of timing
inputs available to train the local oscillator, varies per platform. The priority order of these
references must be specified. This is a simple ordered list of inputs: {ref1, ref2, bits (if available)}.
The CPM clock output shall have the ability to drive the clocking for all line cards in the system.
The routers support selection of the node reference using Quality Level (QL) indications. The
recovered clock will be able to derive its timing from one of the references available on that
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