System Basics Introduction
Page 232 7210 SAS M, T, X, R6 Basic System Configuration Guide
Figure 18: PTP Slave Clock and Master Clock Synchronization
Timing Computation
When using IEEE 1588v2 for distribution of a frequency reference, the slave calculates a message
delay from the master to the slave based on the timestamps exchanged. A sequence of these
calculated delays will contain information of the relative frequencies of the master clock and slave
clock but will have noise component related to the packet delay variation (PDV) experienced
across the network. The slave must filter the PDV effects so as to extract the relative frequency
data and then adjust the slave frequency to align with the master frequency.
When using IEEE 1588v2 for distribution of time, the 7210 SAS uses the four timestamps
exchanged using the IEEE 1588v2 messages to determine the offset between the 7210 SAS time
base and the external master clock time base. The 7210 SAS determines the offset adjustment and
then in between these adjustments, it maintains the progression of time using the frequency from
the central clock of the node. This allows time to be maintained using a Synchronous Ethernet
input source even if the IEEE 1588v2 communications fail. When using IEEE 1588v2 for time
distribution, the central clock should at a minimum have the PTP input reference enabled.
Slave
t1, t2, t3, t4 are measured values
t2 - t1 = Delay + Offset = 51 - 44 = 7
t4 - t3 = Delay - Offset = 57 - 56 = 1
Delay = ((t2-t1) + (t4 - t3))/2 = 4
Offset = ((t2 - t1) - (t4 - t3))/2 = 3
O = Offset = Slave - Master
O D
40
D = Delay
OSSG644
42
44
46
48
50
52
54
56
58
60
62
64
Master
40
42
1t 44
38
46
48
50
52
54
56
58
t2
60
62
t3
t2
Sync
Follow_up (t1)
Delay_req
Delay_resp (t4)