Spyder3 SG-34 GigE Vision Color Manual 21
Teledyne DALSA 03-032-20124-00
TTL Inputs and Outputs
Figure 11: TTL Input Schematic
Termination: 1000 Ω series
Input current: minimum 0 nA; maximum 2 mA
Input voltage: maximum of low 0.66 V; minimum of high 2.6 V
TTL inputs are maximum 5 V and 3.3 V logic tolerant
Figure 12: TTL Output Schematic
Termination: 100 Ω series
Output current: sink 50 mA; source 50 mA
Output voltage: maximum of low 0.55 V @ 32mA; minimum of high 3.8 V @ 32mA.
LVDS Inputs and Outputs (LVDS compliant)
Figure 13: LVDS Input
Figure 14Figure 15: LVDS Output
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