THEORY OF OPERATION
3-16
3-44.
Phase Detector
The 1-MHz reference signal
from divide-by-IO U58, and the
1-MHz
signal from thcN-
divider U17 are connected to
a digital phase-frequency detector
(U43, U44, U45). If the
N-divider output is greater than the
reference frequency, the level at TP38
is high.
When
the output of the level shifter
Q
16
is
above
ground, then CR12 is turned off. This allows
current from
Q
1 9
to flow through
CR 1 3 into the integrator,
decreasing the voltage at the
integrator output, U48 Pin
6,
which
then lowers the frequency of the
VCO until
the
reference and the N-dividcr output are the same
frequency.
Similarly, if the N-divider output frequency
is
below the reference, TP39
is low, and the
voltage at the output of level shifter
Q
1 7
is
below ground, turning off
CR
1 5 and allowing
current from R 108 to flow through CRM
out of the integrator. This
raises
the voltage at
the output of the integrator, which
raises the VCO frequency.
The
phase-frequency
detector
is designed
so that if the phase between the
reference
and N-Divider output
slips
more than two cycles in either direction, the
corresponding phase-detector
output is high
or low. This provides twice
the
integrator current during
acquisition
as
a conventional
phase-frequency
detector.
R107 provides
a
small
bias current
to the integrator
to
bias the
phase detector at
approximately
2,5 radians; consequently, the
down-pump is normally always
on. If the
up-pump comes on, indicating an
over-modulation
condition, the
pulses are detected by
the one-shot,
U47
that
produces the UNLOK .status
that
is then sensed by the Controller.
For flat FM response, it is necessary
for
the PLL bandwidth to
be
constant
ai all VCO
frequencies. Two factors cause
the loop
bandwidth to change; the
VCO
tuning coefficient
(Kv) and the divider ratio
(N).
During
calibration
of the VCO, the Kv is
measured
at many frequencies
across the
band,
and compensation data is stored in the
VCO
Calibration EPROM.
The instrument
software uses this data along with N
to
control the PLL
bandwidth
in a compensating
manner. The PLL
bandwidth
is controlled by changing
the current to the down-pump
via
the KN DAC, U27, and the voltage-to-current
converter,
U46,
Q18,
and
Q19.
3-45.
Loop Amplifier
The loop amplifier-integrator consists of
operational
amplifier
U4S, Cl 18
and R91.
Capacitors C121 and Cl 19 filter the 1-MHz
reference. The output of the
integrator is
connected to a multi-pole LC filter (R92,
C123, C99, C124, C126,
C125, L49, L50, and
R93) that attenuates the delete
rate
(20
and 40 kHz) and
reference
1-MHz spurs.
Diodes CR9 and CRIO stabilize the loop
during switching. The filter
i.s
buffered by the
Darlington emitter-follower
Q20,
which is biased at
10
mA
by
Q21,
Additional lead/lag
compensation
is
provided by R99, RlOl, and Cl3i.
Proper
termination for the filter
is
provided
by R93 and
Q22.
The voltage
for
the loop amplifier
is regulated
to
approximately -I-30V by
Q15.
Amplifier U49 is a precision
clamp to keep the
VCO
frequency above a minimum
value
for oscillation,
and below a maximum above
which the N-divider would not
divide
correctly. The photoisolator
U50 detects when the clamp
is
active, indicating an out-of-
lock condition.
This
signal is ORed with the
signal
from one-shot U47 and sent
to the
microprocessor
as the UNLOK status.
3-46.
FM
PROCESSING
To provide FM
accuracy,
the FM signal FMV from the
Output board is first processed
by
the KV DAC
(U2S,
and
U29) to compensate for the
VCO
tuning coefficient. The KV
DAC setting
is proportional
to
1
/
Kv, where Kv is the
tuning
coefficient. This correction
f
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