Fluke 6060B - Synthesizer PCA; 10 Mhz Reference; Main Phase-Lock Loop

THEORY
OF
OPERATION
3-38.
MODULE SECTION,
A2
The
module section
consists of a
cast
module frame
with gasketed
covers and
includes
the
following
electrical
assemblies:
A2A1,
Synthesizer
A2A2,
VCO
A2A4,
Output
A2A5,
Attenuator/
RPP
A2A7,
Controller
A2A8,
Non
Volatile
Memory
3-39.
Synthesizer PCA,
A2A1
The Synthesizer
PCA
provides
frequency
control
and modulation
of the Signal
Generator output.
The Synthesizer
assembly is
located
on the top
side of the Module
Section
A2. Together with
VCO
A2A2
and
a lO-MHz
reference frequency,
the
Synthesizer assembly
simultaneously
generates
a
high-band
signal that
spans
490 to 1050
MHz and a
mid-band
signal that
spans 245 to 512
MHz.
The
high-band
and
mid-band
signals are
coupled to the
Output A2A4,
Here,
heterodyning
extends
the Generator
frequency coverage
down to O.Ol
MHz.
The
Synthesizer
assembly consists
of the following
functional circuits
that are described
in the
following
paragraphs:
10-MHz
Reference
Mam PLL
FM
Processing
800/40
MHz PLL
Sub-Synthesizer
3-40.
1 0-MHZ
REFERENCE
The
Generator
reference
is the internal
10-MHz
crystal
oscillator.
If
Option
-130
High-
Stability
Oscillator
or
Option
-132
Medium-Stability
Oscillator is
installed,
that
oscillator
is locked
to the internal
crystal oscillator.
An external
reference
of
1
,
2,
5,
or 10
MHz can
also
be locked
to
this oscillator.
The internal
10-MHz
crystal oscillator
(XO) is a
crystal,
Y1
,
and an FET
transistor,
Q39.
The frequency
is adjusted
by C240 and R230.
The oscillator
signal from
Q39
is
buffered
by
Q40,
converted
to
TTL by
U55-B,
and sent to
the sub-harmonic
phase detector,
U68,
and the rear
output through
a 10-MHz
band-pass filter,
C247, L73.
The
lO-MHz
reference
is also
sent
to the
800/40-MHz
loop-phase
detector, the
main loop-phase
detector via
dividc-by-10,
U58,
3-41.
MAIN PHASE-LOCK
LOOP
The
main phase-lock
loop (PLL) is a
fractional
divider
PLL
with a single-sideband
mixer
(SSB) in the
feedback path.
The
oscillator for
this loop is a
.separate
PCA, the A2A2
VCO.
All the remaining
PLL circuitry
is on
the synthesizer
PCA
A2AL
The
key
signals to the
main
PLL are the
I-MHz reference
signal from the 10-
MHz
Reference circuit, the
245-MHz to 512-MHz
signal from the
binary divider,
and the
20-
kHz to 40-kHz
signal
from the sub-synthesizer
circuit. The
fractional division
technique
provides 20-kHz
frequency
resolution.
I
I
I
I
i
i
I
I
i
3-10