THEORY OF
OPERATION
3-26
3-69.
Sub-Harmonic Reference (Part of A2A1)
Comparator
U67
forms an
ac-to-TTL
converter. Diode CR20 and CR21 precondition
the REF IN signal to protect the comparator. Resistors RMS, RI49, R153, and R2I7
provide hysteresis, preventing oscillation
when there is
no input.
MOS
switch
U70 connects the control voltage of the lO-MHz crystal oscillator to a bias
network R229, R230, and R231, or to the loop amplifier, thus closing a
phase-locked
loop.
The phase detector and loop amplifier are made up of U68,
Q26, Q27, Q28,
and U69. The
signal from the
external
reference input through the ac-to-TTL converter or the
enhanced stability options
is
applied
to
the
flip-flop
clock input, U68-3, via U54. The
10-MHz signal from the crystaloscillatorgoes to the other flip-flop clock
input,
U68-1 1.
The flip-flops are connected
,
so the width of the pulse that switches
Q38
is the difference
in time of these two signals
(U68-3 and U68-1
1
). The phase-detector operating point is set
by R223 and R224.
The
output
of
the
loop
amplifier
is
applied
as the
control
signal
to
the
frequency
control
input
of the 10-MHz crystal oscillator through the control
switch
U70. The control
switch,
U70, is controlled by the Generator Controller through the control line SHENL.
This line is enabled when rear panel REF INT/EXT
switch is
set to EXT or when the
enhanced stability options are present.
An out-of-lock
detector
is formed with one-shot U71 . The out-of-lock detector provides
a status output to the Controller that indicates
the lO-MHz oscillator is not locked. An
out-of-lock condition causes the loop amplifier to have a low-frequency
beat note which
triggers the
one-shot
to act as a pulse stretcher.
The output
of the one-shot is an active-low signal and is combined through
diode CR29
with other signals to form the UNLOK. status
signal.
3-70.
NON VOLATILE MEMORY A2A8
3-71.
Power
Circuit
There are two
sources
of power for the Non-Volatile Memory RAM
IC. These
are the
battery and the regulated +5V
Signal Generator supply. Diodes CRl and CR2
form
a
basic diode switching circuit that
allows
the power source with the higher voltage to
provide
current to the CMOS RAM and isolate the other
power source.
Q1
and
Q4
are turned on by
Q2
and
Q3
when the
+5V
supply is above the threshold
voltage set
by
VRI,
R2, and R3.
Q1
has a low collector saturation
voltage. When it is
turned on, the supply voltage
to the CMOS RAM is very dose to
+5
V. The output of
Q4
is the power valid
signal. The CMOS RAM cannot
be
accessed
until the output of
Q4
goes high,
3-72.
Memory
Control
All address,
data,
and control lines to the
CMOS
RAM are
buffered. The enable signals
WEL, DBINL, and
the CMOS RAM are buffered with open-collector
gates. These
signals are held at the
same
potential as the CMOS RAM supply when the +5V supply
goes down, ensuring the
CMOS
RAM
draws the
minimum standby current.
The presence of the
Non-Volatile Memory is detected by the microprocessor when
the
option is plugged into the
Controller
board. The signal NVMENL, normally at +5V, is
pulled to
ground
when the option is installed.
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