THEORY OF
OPERATION
The SSB
mixer, in
conjunction with
the sub-synthesizer,
provides
additional
5-Hz
resolution at
the Synthesizer
frequency. This
corresponds to 10-Hz
resolution on the
high
band.
The main
PLL
consists of
the VCO, the binary divider,
the
SSB
mixer, the
triple-modulus
prescaler, the
N-Divider, the
phase
detector, and the loop
amplifier. All but the VCO
are
described in the
following
paragraphs.
The VCO is discussed
in paragraphs
3-48.
3-42. Binary Divider
And Single-Sideband
Mixer
The
490-MHz to
1050-MHz signal from
the VCO
via J107 is
coupled
to the binary
divider, U
1 . Regulator
Q
1
provides +5V for
the
divider. One output of U
1 is coupled to
the
Output
PCA, A2A4
through
J 104. The other output
is
amplified by
Q2
and Q3.
This
signal is split
into two
quadrature (90®
phase difference)
signals
by 3-dB
coupler,
U6.
This signal, and
two other audio
quadrature
signals from U
10,
are
summed
in the double-
balanced
mixers U7 and US
to produce two
double-sideband
suppressed-carrier
signals.
Because of
the phase
relationship
of the outputs of the mixers,
the summing of the
two
composite
signals
(in resistor
network
R21 and R22) results in
the upper-sideband
component
being
suppressed. The
predominate remaining signal
is
the lower-sideband
signal.
The
lower-sideband
signal, spanning
245
MHz to 512 MHz in
20-kHz
steps, is
amplified
by U9
and applied
to the N-Divider
where
it
is
divided down to 1 MHz.
3-43.
N-Divider
The main components
of the N-Divider are:
Triple-Modulus
Prescaler (divide by
20/21/22)
UlS, U19,
and U20
N-Divider
Custom
Gate Array U17
The
triple-modulus
prescaler,
Figure 3-1
,
consists of a
divide
by 10/
1
1
(U20),
divide
by 2
(U 1
8A),
synchronizing
flip-flop (U 1 8B), and
quad NOR gates (U
19).
If
all the inputs (E
1
,
E2, E3,
E4, and E5) to
the
10/
1 1 divider are
low, the prescaler divides by 1
1,
and the total
division to the
output (U20 pin
7)
is
22. If any of the inputs are
high, it divides by
10,
and
the
total division
is
20.
IfinputsEl
andE3
are low, the
modulus
of the
10/11
divider is controlled by
the output
of
the
following
divide by
2
(U18A).
Consequently, the prescaler divides by
10
half the
time and by
1 1 the other
half,
resulting in a divide by 21. U20
contains the ECL to
TTL
converter. U18B
synchronizes the changing
of
the modulus with the
clocking of the
subsequent
stages.
The N-divider
is
clocked by the composite
prescaler output
U18A.
The
operation
of the
triple-modulus
prescaler is shown in
Figure
3-1.
The
prescaler
operates in
conjunction with the
N-divider gate array shown
in Figure
3-2,
3-11
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