Fluke 6060B - Sub-Synthesizer; Vco Pca

THEORY OF OPERATION
3-18
R
198,
and R200
provide isolation
between the
outputs.
The
VCO
signal
is coupled
to the
output
assembly
A2A4 by a
through-the-plate
coaxial
connector
P
108
at the
0 dBm level.
The
other
VCO signal
is connected
to the
divider U6I
to provide the
feedback for the
PIL.
3-49.
SUB-SYNTHESIZER
The sub-synthesizer
consists of the
dock generator,
U34,
35,
Q4,
Q5,
the
gate-array,
U33,
the divide by
500,
U 1
5,
and U
1
6,
and the
low-pass
filter L 1 1
and
L 1 7. Internal
to the sub-
synthesizer
gate-array, U33, are
a divide-by-two,
a 3
1/2 decade-rate
multiplier,
and
a.ssociated
latches.
The
balanced
40-M Hz ECL
clock signal
is
converted
to
TTL in
Q4
and
05,
and converted
to a two-phase 20-MHz
clock in
U34, U35.
An
enable
output of each
section allows
multiple
sections
to be
cascaded.
The input
frequency
to the rate-multiplier
is 20-MHz.
The output
frequency
can be programmed
from zero to 19.995 MHz
in 5-kHz
steps.
This signal
is ORed
with
the other
phase
of the
20-MHz clock
to
produce
20
MHz
to
39.995
MHzat
U33pin
1, This
is
divided
by two in
the
gate-array,
by ten
in U 1
5,
and
again
by 50 in
U 16 to
produce
20
kHz
to
39.995 kHz
in
5-Hz steps.
This
TTL signal
at TP 1 1 is filtered
by L 1
1 ,
H
7,
and C4
1 ,
C42, C48, C50, and
C51.
Op-amp, UlO forms
an active
quadrature
generator,
and the
output pins 14
and 8
are
offset by
90*.
These
two signals
are the 20-kHz
to 40-kHz
inputs for the
Main PLL
single-sideband
mixer.
3-50.
VCOPCA,
A2A2
The VCO PCA
A2A2
is the heart
of the main
PLL. It
produces
the signal
that is further
processed to
become the
Signal
Generator
output. The
VCO
assembly
is located in a
bottom side
compartment
of
the Module
section A2.
The
VCO
tunes over
a frequency range
of 490
MHzto
1050 MHz
with a control
voltage
range of +2V to +18V.
The basic
oscillator
circuit
uses
two active
devices
operating
as
negative
resistance
dements.
Coupled
symmetrically
to a resonator,
each active
device
is
followed
by a 6-dB
amplifier
and a
I5-dB isolator
pad that
provides two
coherent
but
isolated
signals
at
about 0 dBm.
One signal is sent to
the Output
A2A4
assembly,
and the
other
to the
Synthesizer
A2A1
assembly.
To
suppress harmonics,
two tuned
trap filters
are placed
between
the negative
resistance
devices and
amplifiers
Q2 and
Q4.
The oscillator
transistors
Ql and
Q3
are biased
at 13 mA
by the FET
current
sources
Q5
and
Q6.
The voltage
at the
collectors
of
Q
1
and
Q3
are
typically
set at
+6V. The two
6-d
B
amplifiers
Q2
and
Q4
are biased
so that the
voltage at their
emitters
is about
-hO.3 V and at
their bases
about
-KV, with the
collectors
at about
+6,5V,
The PLI.
control voltage
from the
Synthesizer
assembly A2A
I at P102
provides
the
tuning
voltage for
varactors
CR
1 and CR2. This
voltage
also
controls varactors
CR3 and
CR4 with
resistors
R6, R4,
RI8,
R19,and R20.
These
varactors,
in
conjunction
with their
lead
inductance
and
C 1 and C32, make
up a shunt
trap filter at
twice
the VCO
frequency
to suppress the
in-band
second
harmonic
at
both VCO
outputs
to typically
less
than
-10
dBc,
The
output attenuators
consisting
of R13, R14,
R15, R27,
R28, and R29
provide the
isolation
between
the two
VCO
outputs at P
103 and PI04,
C23 and C30,
in
series with the
printed
board inductors,
form
out-of-band
trap filters
for
approximately
1 .4 GHz.
These
filters
further
suppress
the out-of-band
harmonics.
I
I