Fluke 6060B - Page 98

THEORY
OF OPERATION
The N“Divider gate-array contains
two 5-bit binary counters
(A and N), a BCD two-
decade rate multiplier, and latches
to interface
to the
microprocessor.
The operation of
the N and A counters is as
follows:
At the beginning of a count
cycle, a number is
loaded
into the A and N
counters. The A
counter is not at its terminal
count, so the output
is
high,
and the mode line
(MODE L) is
low. This causes the prescaler
to divide by
21
(or
22,
TRMODL
=
low).
The
mode line
Stays low for 31-A counts,
where
A is the programmed
number. The mode line
goes high,
and the prescaler
divides
by
20
(or
21,
TRMODL
=
low) for 3\-N
counts.
The total
division is;
(P+l)*(31-A) T
P*((31-N)-(31-A))
or
P*(31-N)
+
(31-A)
On the 3 1 st count, the
counters
are reinitialized.
Figure 3-3
shows the timing
for the
A-
counter programmed
to
26,
and the N-counter
programmed to 18. Only the
CKNLand
MODE
L signals shown in
Figure
3-2
are accessible
at
UI7,
pin
6,
and
22,
respectively,
Figure
3-3
show
the N-Divider
timing
diagram.
The N-Divider
gate array includes a two-decade
rate multiplier that
produces
the
fractional part of the division. It produces
a pulse train with a
programmed
number of
pulses for a 100-cycle frame
of the
1-MHz N-divider output.
The programmed
number
ranges between zero and
98 in steps of two,
corresponding
to
20-kHz steps at the mid-band
output frequency, The
flip-flops
in the rale multiplier
get
setup on count
29,
and on count
30,
a
pulse
may or may not
be
present depending on the
programming of the rate multiplier.
This is the shaded pulse in
the timing diagram, Figure
Irregularly spaced
rate-multiplier
pulses cause the
mode line to go low, and
the prescalcr
divides
by
P4-1
at a rate equal to the rate multiplier
programming. At a
division of
255,
the N and A
counters
are normally programmed
to 1 5. This means the
divider
is always
dividing
by
21;
consequently,
there is no place
to slip in the rate-multiplier
pulses.
It might be noted
that
a
20/
21 dual-modulus
prescaler
will not allow division
from
245 to
525
without
holes. For example
252
is 0 frames of 20 and 1 2
frames
of 2 1 . Consequently,
there is no place
to slip in the rate-multiplier
pulses. It is not possible
to
divide by 253.
By using a
triple-modulus
prescaler, these
problems
are solved. Continuing
with the
previous
example 252 is 12
frames
of 21 and 0 frames
of
22,
The deleter functions
by
allowing the
prescaler
to divide by 22
at a rate equal to the rate-multiplier
frequency.
Number
253 is 1 1
frames
of 21 and 1 frame
of
22,
A software algorithm
determines
whether
to
operate in the
20/21
mode (TRMODL
=1)
or
21/22
mode (TRMODL =0).
The frequency at the output
of the N-divider gate array,
is
(Fo/ 2
-
Fs
-
Fd)
/
N; where
Fo is
the VCO
output
frequency, Fsis the
sub-synthesizer frequency,
and Fd
is the fractional-
division frequency.
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ill
II
I
I
3-14