Theory  of  Operation 
DC 
SCWNG 
positive supply is approximately 6.2V  above the input and 
conversion cycle. The circuit also provides a gain ot 10 in 
the  negative  supply 
is 
approximately  6.2V  below.  the  200 mV 
dc, 
20052,  and  2000 
mA 
dc ranges., 
5-6. 
VDC  Protection 
The circuit operates by  cycling between the 
track, 
stjttling, 
hold,  and precharge  configurations shown in  Figurk 
5-4. 
Input protection for the 
M)C 
function is provided by  a 
lK, 
me In-Gmd 
& 
selects a  particular  settling 
and 
hold 
fusible resistor (R309),  four metal-oxide varistors (MOVs) 
configuration for each function and range, 
and 
su 
esses 
(RV301,  RV402,  RV403,  and  RVW),  and  additional 
the pecharge configuration for eatain ranges. Thi$trol 
protection  resistors and  clamp  circuits. 
is 
achieved 
by  latching function and range informatton in 
U301,  U302,  and  U303. 
WARNING 
TO  AVOID  INJURY  OR 
EQUIPMENT 
DAMAGE, 
USE 
EXACT  REPLACEMENT 
PARTS  FOR 
ALL 
PROTECTION  COM- 
PONENTS. 
I 
Basic timing for the 
TM 
circuit  is provided  by  th% 
AD 
Converter over clock lines 
PC, 
HD1, TRl, and TR21 (See 
the timing diagram in Figure 5-5,  top.)  The 
T/H 
c$cle 
is 
initiated when  the In-Guard 
pC 
pulls  line 
TR 
low. 
5-10.  Tmk Configuration 
In the track  configuration (Figure 5-4A),  the 
TRI 
Frcuit 
In 
dc 
greater 
than 
fun- 
as 
a non-inv&ng  buffer. The volage  on 
,008 
1560V are clamped by  the MOVs.  Extreme  overvoltage 
track 
scaled 
dc 
input 
voltage- 
conditions cause 
R309 
to  fail  open-circuit. 
R309 
is followed either by  a 
99 
kQ,  10W resistor network 
(2304) in the 
200 
mV,  2V, and 20V  ranges, or by  10 
MQ 
(2302)  to ground  in  the 200V and  lOOOV  ranges. 
2304 
provides  current  limiting in  extreme  overvoltage condi- 
tions  in  the  200  mV,  2V,  and  20V  ranges.  The  non- 
5-1 
1. 
Settling 
Configuration 
The circuit assumes a  settling configuration betwwn the 
track  and  hold  configurations.  The  circuit 
assumds 
the 
configuration &Figure 5-4B for 
unity 
gain and the cbnfig- 
uration  in  Figure  5-4C  for  gain  of  10. 
inverting input of  U306 is clamped to +25V by  Q307 and 
Q308. 
5-7. 
mA 
DC 
Scaling 
In  the 
mA 
DC 
function,  the  unknown  current 
causes 
a 
voltage drop across current shunt R319. This voltage drop 
is then measured 
as 
in the VDC function. The 
DC 
Scaling 
circuit  is configured 
as 
shown  by  the  simplified switch 
table  in  Figure 5-2. 
M. 
Analog Filter 
The 
three-pole, low-pass analog filter (U304) 
has 
a Butter- 
worth  response  with  comer  frequency  at  7 
Hz, 
giving 
approximately 50 
dB 
of  rejection at  50 
Hz. 
The filter is 
used only for the slow reading rate and is used only in the 
VDC 
ranges 
and 
lowest three ohms ranges.  The filter  is 
switched into the input signal path by 
Q304 
(Figure 5-2). 
In  some ranges and functions, additional filtering is  pro- 
vided  by  U302B  and 
C314. 
During this time the 
DC 
Scaling circuit is still coqected 
to  the 
T/H 
amp.  However, changes in  the input 
cib 
not 
affect the value to 
be 
measured, which is stored on 
(3308. 
5-12 
Hold 
Configuration 
The 
X1 
hold configuration (Figure 54D) 
is 
used  fior 
all 
VDC 
ranges except rl and for all ohms ranges exvt rl. 
The output  of  U307  is the negative of  the input vqltage. 
The XI0 hold configuration (Figure 5-4E) 
is 
used fbr the 
mA 
DC 
function,  the  200  mV  dc  range,  and  the 
b0052 
range,  and provides  a  gain  of  10. 
5-13.  Pre-Charge Configuration 
The  pre-charge  configuration (Figure 
5-4F) 
occurs 
I 
after 
the hold  configuration in VDC  ranges rl, r2,  and r4,  and 
ohms ranges  11,  r2,  r3,  and  r4.  U306  is connectd, 
as 
a 
buffer  to  charge  stray  capacitance  at  the  non-inverting 
input  of  the 
T/H 
Amplifier. The pre-charge configuration 
is not  used  in  any  other  ranges. 
5-9. 
TRACWHOLD CIRCUIT  5-14.  PRECISION 
VOLTAGE 
REFERENCE 
The TracWold 
(Tm) 
circuit presents 
a 
stable voltage to 
The  Precision  Voltage  Reference  (Figure  5-6)  pqvides 
the 
A/D 
Converter  during the  input 
period 
of  the 
AID 
precise reference voltages of  -7.00000  and +7.0000C4.  The 
5-4 
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