~heory
of
in
DIGITAL
GO
UER
address is valid, and the data strobe
(DS)
changes from
low to high when the data is valid.
The address strobe latches the address on ADO-AD7 into
U219 which then provides static address inputs for those
devices that need
it
while data is on the
bus.
The data
memory line
(DM)
divides
the address space between
program memory (U222) and
data
memory (all other
devices on the bus).
The
data memory
address
space is
further divided between the calibration memory (U220)
and the remaining devices
by
All. The addresses of the
remaining devices are decoded from A8-A10 by U208,
which combines the address with the
data
strobe (DS) to
provide a chip select (CSO, CS5 CS3,
CS4,
or
CS7)
for
each device.
The In-Guard WC performs the following functions: range
and function control;
AD
control and computation; cali-
bration corrections; keyboard/display control; serial com-
munication with the IEEE-488 interface; and diagnostic
self-testing and troubleshooting.
5-29.
Function
and
Range Control
-
The
In-Guard
PC
configures the DC Scaling circuit, the
TrackNold circuit, and the Ohms Current Source to pro-
vide the proper input switching, scaling, and filtering for
each function, range, and reading rate. It does this by
controlling dedicated output lines which control relays and
FET
switches, and by sending configuration codes out on
the bus. The quad analog switches (U301, U302, U303,
U402,
and U403) latch the configuration codes and per-
form any level-shifting needed to control their internal
MOSFET switches. Some of the switches require dynamic
timing signals from the custom
AID
IC (U101); these
signals are combined appropriately in the quad analog
switches with the configuration codes.
5-30.
AJD
Control
and
Computation
The In-Guard pC initiates each
AD
sample by pulling line
TR
low. When the pC is reset, it senses the power line
frequency on line FREQ REF. The pC then sets its
internal timer so that the
A/D
sample rate is
as
shown in
Table
5-1.
The number of readings per second for the slow and
medium rates are chosen to provide rejection of input
signals that
are
at the line frequencies.
the
CcC
and sent for display. With internal trigge
AD
runs continuously at
$0
samples per
reading being sent to the display every
5-31.
Cglibration Correction
I
The
calibration
constants used by the ln-Guardl
CIC
in
computing
each
reading are stored in the EERO (elec-
tronically erasable read-only
memory)
Calibration ternov
(U220). The front panel CAL ENABLE switch rotects
the EEROM from accidental writes.
I
,
5-32.
KeyboardDiipiay
Control
I
KeyboardYDisplay Controller U212 communicates
In-Guard VC over the intanal bus. During a
cycle, awes line A0 tells U212 whether to
being
sent by the WC
as
configuration
display data. Display
data
is stored in
play Controller, which
The
KeybaarWisplay Controller
using decoder U213 and buffer
buffered by U218.
data
is decoded from
BCD
to 7-segment
by
decode$
U216
and
buffqred by U217.
Additional
annunciator bta is
I
I
I
The Keyboardfisplay Controller is reset by the
I*Q
when-
ever the
pC
is reset. It receives a
1
MHz
clock sign from
the custom
AD
IC (UlOl), which uses the PC
!MHz
crystal for its clock input.
The KeyboarWisplay Controller
scans
the
sensing
pressed
buttons on lines RLO-RL7. It
interrupt
40
the
C1C
via line KEYINT
panel button
is
pressed. The
&
then
from the Keyboard/Display Controller.
FRONT/REAR switch is sensed separately
by
~ibe
F/R
SENSE.)
I
5-33.
Troubleshooting
Modes
In addition to running the diagnostic self-tests,
Guard pq has a troubleshaoting mode which
finding digital hardware problems. After
the
PC
is
senses the relay control lines (U202-35 through U
as
inputs. If line U202-38 (TP205)
is
shorted to
the
pC
goes into the troubleshaoting node.
vides int&rnai pull-up.) The troubleshooting mpde is
described
in detail in the Maintenance section.
I
I
5-34.
Guard-Crossing Communication
1
The custom
AID
IC (U101)
after each trigger from the pC and
The In-Guard
pC
contains a UART (universal
telling
the
CLC
that
data
is
ready.
The
five read cycles) and computes the value of the
A/D
&bit numbers over the bus
(~s7
pulses
I
sample using calibration coktants. The averages the
5s.
appropriate number of samples for one reading, which
is
then sent to the keyboard/display interface for display.
The Guard Crossing consists of two identical circui
of which transmits data
in
one direction across th
For example, with a 60-Hz power-line frequency,
an
exter-
isolation between the Main Printed Circuit ksemdly and
nally triggered reading in the slow reading rate would the IEEE-488 Interface. One circuit is shown in Figure
cause the
PC
to send 32 pulses on
TR
at
an
80
Hz
rate.
5-15;
the other circuit works identically.
A
portion ?f each
The 32
AID
samples would
be
calibrated and averaged by circuit is contained in the IEEE-488 Interface.
I
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