GE LPS-O - Page 111

GE Power Management LPS-O Line Protection System 3-
15
3 HARDWARE DESCRIPTION 3.3 PRINTED CIRCUIT BOARD MODULES
3
Figure 3–11: BLOCK DIAGRAM OF THE SYSTEM PROCESSOR (i960 CPU)
EEPROM
32K x 8
CAP-
BACKED
REAL
TIME
CLOCK
TIMER
COUNTER
CAP-
BACKED
RAM
128K x 16
(512K x 16)
i960
PROGRAM
FLASH
MEMORY
STATIC
RAM
WDT
CLOCKOUT
COUNTER
CLOCK
GENERATOR
24.576 MHz
INTERRUPT
ENCODER
SYS-DAT
TRANSCEIVER
BUFFER
MEMORY
CONTROLLER
SYS-ADD
BUFFER
RESET
CLOCK
ADDRESS
DATA
CONTROL
XINT
BUFFER
LATCH
TRANSCEIVER
LOCAL DATA BUS
LOCAL ADDRESS BUS
DATA BUS
PIPELINED / BURST
ADDRESS BUS
SYSTEM ADDRESS BUS
CHIP SELECTS
BYTE ENABLE
SIGNALS
SYSTEM BUS
CONTROLS
SIGNALS
SYSTEM BUS
INTERRUPT