200 IBM eX5 Implementation Guide
fashion to provide a balanced system and populating all processors identically is also
required by VMware.
Looking at Figure 5-16 as an example, Processor 0 has DIMMs populated, but no DIMMs are
populated that are connected to Processor 1. In this case, Processor 0 has access to
low-latency local memory and high-memory bandwidth. However, Processor 1 has access
only to remote or “far” memory. So, threads executing on Processor 1 have a longer latency to
access memory as compared to threads on Processor 0. This result is due to the latency
penalty incurred to traverse the QPI links to access the data on the other processor’s memory
controller. The bandwidth to remote memory is also limited by the capability of the QPI links.
The latency to access remote memory is more than 50% higher than local memory access.
For these reasons, we advise that you populate all of the processors with memory,
remembering the necessary requirements to ensure optimal interleaving and Hemisphere
Mode.
Figure 5-16 Memory latency when not spreading DIMMs across both processors
5.10.4 Memory mirroring
Memory mirroring is supported using HX5 and MAX5. On the HX5, when enabled, the first
DIMM quadrant is duplicated onto the second DIMM quadrant for each processor. For a
detailed understanding of memory mirroring, see “Memory mirroring” on page 28.
This section contains DIMM placements for each solution.
DIMM placement: HX5
Table 5-17 on page 201 lists the DIMM installation sequence for memory-mirroring mode
when one processor is installed.
QPI links
Intel Xeon 7500
Processor 0
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMMDIMM
Buffer Buffer Buffer Buffer
Memory
controller
Memory
controller
Intel Xeon 7500
Processor 1
DIMM
DIMM
DIMMDIMM
Buffer Buffer Buffer Buffer
Memory
controller
Memory
controller
LOCAL
REMOTE
Important: If using memory mirroring, all DIMMs must be identical in size and rank.
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