Chapter 6. IBM System x3850 X5 and x3950 X5 239
stand-alone database server with built-in fault tolerance for power and cooling, processors,
memory, and PCIe buses.
6.6.1 Generation 2 and Generation 1 PCIe adapters
All of the PCIe slots in the x3850 X5 are at Generation 2 (Gen 2) specification. Besides
additional error correction and addressing advancements, Gen 2 means that all of the slots of
this server exchange data twice as fast as servers with Gen 1 PCIe slots.
Table 6-6 describes the theoretical limits of each of the common types of PCIe adapters.
Remember that theoretical limits are based on the mathematics of the frequency and data
width of the bits that are transmitted over the interface. Theoretical limits do not include the
necessary communications to maintain the required protocols to interface between intelligent
devices. Theoretical limits also do not consider the inability to maintain a steady flow of data
in full duplex.
Table 6-6 Theoretical data transfer limits of Gen1 PCIe slot types versus Gen2 PCIe slot types
PCIe adapters connect to the processors via the I/O hub. The purpose of the I/O hub is to
combine the various data streams from each of the PCIe slots into a single aggregate link to
the processors using a dedicated QPI link to each processor. The x3850 X5 has two I/O hubs.
The data transfer rate of the QPI link is negotiated between the processor and the I/O hub.
Table 3-9 on page 74 shows the QPI link speeds based on the type of installed processors.
The I/O hub supports the highest QPI link speed that is shown in the table, 6.4 gigatransfers
per second (GT/s). You can also adjust the QPI link speed to conserve power by booting into
F1-Setup, selecting System Settings ï‚® Operating Modes, and setting QPI Link Frequency
to values other than the default Max Performance, as shown in Figure 6-15 on page 240.
PCIe adapter/slot type Generation 1 Limit Generation 2 Limit
x1 500 MBs 1 GBs
x4 2 GBs 4 GBs
x8 4 GBs 8 GBs
x16 8 GBs 16 GBs
x32 16 GBs 32 GBs
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