Intel 5000 Series User Manual

Functional Architecture Intel® 5000 Series Chipsets Server Board Family Datasheet
Revision 1.1
Intel order number D38960-004
10
2.1.2.7 Low Pin Count (LPC) Interface
The Intel
®
631xESB / 632xESB I/O Controller Hub implements an LPC Interface as described in
the Low Pin Count Interface Specification, Revision 1.1. The low pin count (LPC) bridge function
of the Intel
®
631xESB / 632xESB I/O Controller Hub resides in PCI Device 31: Function 0. In
addition to the LPC bridge interface function, D31:F0 contains other functional units including
DMA, interrupt controllers, timers, power management, system management, GPIO, and RTC.
2.1.2.8 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte
transfers, and channels 5 through 7 are hardwired to 16-bit, count-by-word transfers. Any two of
the seven DMA channels can be programmed to support fast Type-F transfers.
The Intel
®
631xESB / 632xESB I/O Controller Hub supports LPC DMA. LPC DMA and PC/PCI
DMA use the Intel
®
631xESB / 632xESB I/O Controller Hub’s DMA controller. LPC DMA is
handled through the use of the LDRQ# lines from peripherals and special encoding on LAD[3:0]
from the host. Single, demand, verify, and increment modes are supported on the LPC
interface. Channels 0–3 are 8 bit channels. Channels 5 through 7 are 16-bit channels. Channel
4 is reserved as a generic bus master request.
The timer / counter block contains three counters that are equivalent in function to those found
in one 82C54 programmable interval timer. These three counters are combined to provide the
system timer function, and speaker tone. The 14.31818-MHz oscillator input provides the clock
source for these three counters.
The Intel
®
631xESB / 632xESB I/O Controller Hub provides an ISA-compatible programmable
interrupt controller (PIC) that incorporates the functionality of two 82C59 interrupt controllers.
The two interrupt controllers are cascaded so that 14 external and two internal interrupts are
possible. In addition, the I/O Controller Hub supports a serial interrupt scheme. All of the
registers in these modules can be read and restored. This is required to save and restore the
system state after power has been removed and restored to the platform.
2.1.2.9 Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA-compatible PIC described in the previous section, the Intel
®
631xESB / 632xESB I/O Controller Hub incorporates the Advanced Programmable Interrupt
Controller (APIC).
2.1.2.10 Universal Serial Bus (USB) Controller
The Intel
®
631xESB / 632xESB I/O Controller Hub contains an enhanced host controller
interface that supports USB high-speed signaling. High-speed USB 2.0 allows data transfers up
to 480 Mb/s, which is 40 times faster than full-speed USB. The I/O Controller Hub also contains
four universal host controller interface (UHCI) controllers that support USB full-speed and low-
speed signaling.
The Intel
®
631xESB / 632xESB I/O Controller Hub supports eight USB 2.0 ports. All eight ports
capable of high-speed, full-speed, and low-speed.

Intel 5000 Series Specifications

General

Brand	Intel
Model	5000 Series
Category	Server Board
Language	English