Intel Agilex Series User Manual

Figure 41. AS Configuration Serial Input Timing Diagram
nCSO
AS_CLK
AS_DATA IN0 IN1 INn
T
ext_delay
Table 34.
T
ext_delay
as a Function of AS_CLK Frequency
Symbol Configuration Clock Source Frequency Min (ns) Max (ns)
T
ext_delay
Internal Oscillator 115 MHz 0 20
77 MHz 0 20
58 MHz 0 20
25 MHz 0 24
OSC_CLK_1 166 MHz 0 13.5
125 Mhz 0 18
100 MHz 0 24
71.5 MHz 0 35
50 MHz 0 24
25 MHz 0 24
Note: For more information about the timing parameters, refer to the Intel Agilex Device Datasheet.
3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines
You must minimize the skew on the AS data pins.
3. Intel Agilex Configuration Schemes
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Configuration User Guide
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Intel Agilex Series Specifications

General

Architecture	FPGA
AI Tensor Blocks	Yes
Category	FPGA
Family	Agilex
Transceiver Speed	Up to 112 Gbps
Manufacturer	Intel
Series	Agilex
Transceiver Data Rate	Up to 112 Gbps
Memory Support	HBM2E
PCIe Support	PCIe 5.0
Memory	HBM2e
Power Efficiency	Improved over previous generations
Operating Temperature	Commercial, Industrial
Process Technology	10nm