5.6.1. Prerequisites
To run this remote system update example, your system must meet the following hardware and software requirements:
• You should create and download this example to the Intel Agilex SoC Development Kit.
• Your design should include the Mailbox Client Intel FPGA IP that connects to a JTAG to Avalon Master Bridge as shown the
Platform Designer system. The JTAG to Avalon Master Bridge acts as the remote system update host controller for your
factory and application images.
• In addition, your design must include the Reset Release Intel FPGA IP. This component holds the design in reset until the
entire FPGA fabric has entered user mode.
•
The ninit_done_reset and reset_bridge_1 components create a two-stage reset synchronizer to release the
Mailbox Client Intel FPGA IP and JTAG to Avalon Master Bridge Intel FPGA IP from reset when the device configuration is
complete and the device is in user mode.
5. Remote System Update (RSU)
683673 | 2021.10.29
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