Intel Agilex Series

Related Information
An Essential Reset for Intel Stratix
®
10 and Intel Agilex Devices
4.1. Understanding the Reset Release IP Requirement
Intel Agilex devices use a parallel, sector-based architecture that distributes the core fabric logic across multiple sectors.
Device configuration proceeds in parallel with each Local Sector Manager (LSM) configuring its own sector. Consequently,
FPGA registers and core logic do not exit reset at exactly the same time, as has always been the case in previous families.
The continual increases in clock frequency, device size, and design complexity now necessitate a reset strategy that considers
the possible effects of slight differences in the release from reset. The Reset Release Intel FPGA IP holds a control circuit in
reset until the device has fully entered user mode. The Reset Release FPGA IP generates an inverted version of the internal
INIT_DONE signal, nINIT_DONE for use in your design.
4. Including the Reset Release Intel FPGA IP in Your Design
683673 | 2021.10.29
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Configuration User Guide
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