Intel Agilex Series

3.1.5. Avalon-ST Single-Device Configuration
Figure 17. Connections for Avalon-ST x8 Single-Device Configuration
Intel FPGA
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
OSC_CLK_1
MSEL[2:0]
AVSTx8_DATA [7:0]
AVSTx8_VALID
AVSTx8_READY
AVSTx8_CLK
Configuration
Data Signals
Configuration
Control Signals
Non-Volatile Memory Interface
External Non-Volatile Memory
Access Port
.rbf or .pof
CPLD / FPGA
External Host
fpga_clk
fpga_ready
fpga_valid
fpga_conf_done
fpga_nstatus
fpga_nconfig
fpga_data [7:0]
Parallel Flash Loader II IP
or
Microprocessor
or
Custom Logic
10kΩ
MSEL
V
CCIO_SDM
8
3
External Clock Source (Optional)
(2)
(1)
10kΩ
V
CCIO_SDM
3. Intel Agilex Configuration Schemes
683673 | 2021.10.29
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