Intel Agilex Series

• Verify that the host device does not drive configuration pins before the Intel Agilex device powers up.
•
Ensure nCONFIG remains high during the configuration process.
•
Verify that CONF_DONE and INIT_DONE pins correlate to the Intel Quartus Prime SDM I/O pins assignment and the
board-level connections.
•
Ensure that during the power up, no external component drives the nSTATUS signal low.
Related Information
Configuration Debugging Checklist on page 210
3.1.7. IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
3.1.7.1. Functional Description
You can use the Parallel Flash Loader II Intel FPGA IP (PFL II) with an external host, such as the MAX II, MAX V, or Intel MAX
10 devices to complete the following tasks:
• Program configuration data into a flash memory device using JTAG interface.
• Configure the Intel Agilex device with the Avalon-ST configuration scheme from the flash memory device.
Note: Intel Agilex device configuration is not available in the current release.
Note: Use the Parallel Flash Loader II Intel FPGA IP with the Avalon-ST configuration scheme in Intel Agilex devices, not the earlier
Parallel Flash Loader IP.
Note: The current implementation does not support programming two QSPI devices with two separate PFL images in a single
programming cycle. To program multiple QSPI devices, you must program each QSPI flash device with a single PFL image
separately.
Note: The Parallel Flash Loader II Intel FPGA IP does not support HPS cold reset.
Note: The Parallel Flash Loader II Intel FPGA IP will not be able to drive the Avalon streaming interface at the maximum throughput
as described in Intel Agilex Configuration Time Estimation on page 50.
3. Intel Agilex Configuration Schemes
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