7.5. Understanding SEUs
SEUs are rare, unintended changes in the state of an FPGA's internal memory elements caused by cosmic radiation effects.
The change in state is a soft error and the FPGA incurs no permanent damage. Because of the unintended memory state, the
FPGA may operate erroneously until background scrubbing fixes the upset.
The Intel Quartus Prime software offers several features to detect and correct the effects of SEU, or soft errors, and to
characterize the effects of SEU on your designs. LSM firmware provides SEU single bit error and double adjacent bit error
detection and correction. The multi-bit error and non-adjacent bit error are detected, but cannot be corrected. Additionally,
some Intel FPGAs contain dedicated circuitry to help detect and correct errors.
For more information about SEUs, refer to Intel Agilex SEU Mitigation User Guide.
Related Information
Intel Agilex SEU Mitigation User Guide
7.6. Reading the Unique 64-Bit CHIP ID
The Chip ID Intel FPGA IP in each Intel Agilex device stores a unique 64-bit chip ID. Refer to the Mailbox Avalon ST Client IP
User Guide learn how to read the Chip ID from the Intel Agilex device.
Related Information
Mailbox Avalon ST Client Intel FPGA IP User Guide
7.7. E-Tile Transceivers May Fail To Configure
Making the PRESERVE_UNUSED_XCVR_CHANNEL assignment to completely unused E-tile transceivers may cause configuration
failures in Intel Agilex devices.
The Intel Quartus Prime Programmer detects an internal error and fails to configure your device under the following
conditions:
•
You have made the PRESERVE_UNUSED_XCVR_CHANNEL assignment to an entire unused E-tile.
• Your design does not provide a reference clock to this unused E-tile.
7. Intel Agilex Debugging Guide
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