Intel Agilex Series User Manual

7.5. Understanding SEUs
SEUs are rare, unintended changes in the state of an FPGA's internal memory elements caused by cosmic radiation effects.
The change in state is a soft error and the FPGA incurs no permanent damage. Because of the unintended memory state, the
FPGA may operate erroneously until background scrubbing fixes the upset.
The Intel Quartus Prime software offers several features to detect and correct the effects of SEU, or soft errors, and to
characterize the effects of SEU on your designs. LSM firmware provides SEU single bit error and double adjacent bit error
detection and correction. The multi-bit error and non-adjacent bit error are detected, but cannot be corrected. Additionally,
some Intel FPGAs contain dedicated circuitry to help detect and correct errors.
For more information about SEUs, refer to Intel Agilex SEU Mitigation User Guide.
Related Information
Intel Agilex SEU Mitigation User Guide
7.6. Reading the Unique 64-Bit CHIP ID
The Chip ID Intel FPGA IP in each Intel Agilex device stores a unique 64-bit chip ID. Refer to the Mailbox Avalon ST Client IP
User Guide learn how to read the Chip ID from the Intel Agilex device.
Related Information
Mailbox Avalon ST Client Intel FPGA IP User Guide
7.7. E-Tile Transceivers May Fail To Configure
Making the PRESERVE_UNUSED_XCVR_CHANNEL assignment to completely unused E-tile transceivers may cause configuration
failures in Intel Agilex devices.
The Intel Quartus Prime Programmer detects an internal error and fails to configure your device under the following
conditions:
•
You have made the PRESERVE_UNUSED_XCVR_CHANNEL assignment to an entire unused E-tile.
• Your design does not provide a reference clock to this unused E-tile.
7. Intel Agilex Debugging Guide
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Intel Agilex Series Specifications

General

Architecture	FPGA
AI Tensor Blocks	Yes
Category	FPGA
Family	Agilex
Transceiver Speed	Up to 112 Gbps
Manufacturer	Intel
Series	Agilex
Transceiver Data Rate	Up to 112 Gbps
Memory Support	HBM2E
PCIe Support	PCIe 5.0
Memory	HBM2e
Power Efficiency	Improved over previous generations
Operating Temperature	Commercial, Industrial
Process Technology	10nm

Summary

1. Intel Agilex Configuration User Guide

1.1. Intel Agilex Configuration Overview

Overview of Intel Agilex configuration, SDM, and schemes.

1.2. Intel Agilex Configuration Architecture

Details the Intel Agilex configuration architecture, including SDM, network, and LSMs.

2. Intel Agilex Configuration Details

2.1. Intel Agilex Configuration Timing Diagram

Timing diagram for power-on, configuration, and reconfiguration.

2.2. Configuration Flow Diagram

Describes the state transitions during Intel Agilex FPGA configuration.

2.5. Intel Agilex Configuration Pins

Details the configuration pins and their mapping for Intel Agilex devices.

2.6. Configuration Clocks

Covers configuration clock sources and requirements for Intel Agilex devices.

2.8. Generating Compressed .sof File

Generates a compressed .sof file to reduce size and improve configuration speed.

3. Intel Agilex Configuration Schemes

3.1. Avalon-ST Configuration

Describes the fast Avalon-ST configuration scheme using an external host.

3.1.1. Avalon-ST Configuration Scheme Hardware Components and File Types

Components and file types for implementing Avalon-ST configuration.

3.1.2. Enabling Avalon-ST Device Configuration

Steps to enable Avalon-ST configuration in Intel Quartus Prime.

3.1.6. Debugging Guidelines for the Avalon-ST Configuration Scheme

Debugging tips for the Avalon-ST configuration scheme.

3.1.7. IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core

Details the PFL II IP core for Avalon-ST configuration.

3.2. AS Configuration

Details the AS configuration scheme using serial flash devices.

3.2.1. AS Configuration Scheme Hardware Components and File Types

Components and file types for the AS configuration scheme.

3.2.6. Programming Serial Flash Devices

Explains programming serial flash devices using AS interface.

3.2.9. Active Serial Configuration Software Settings

Software settings for AS configuration in Intel Quartus Prime.

3.2.10. Intel Quartus Prime Programming Steps

Steps for programming using Intel Quartus Prime.

3.2.11. Debugging Guidelines for the AS Configuration Scheme

Debugging tips for the AS configuration scheme.

4. Including the Reset Release Intel FPGA IP in Your Design

4.1. Understanding the Reset Release IP Requirement

Explains the necessity of the Reset Release IP for proper reset management.

4.5. Detailed Description of Device Configuration

Details device configuration steps including initialization.

5. Remote System Update (RSU)

5.1. Remote System Update Functional Description

Functional overview of Remote System Update (RSU) for Intel Agilex devices.

5.1.5. RSU Recovery from Corrupted Images

Provides steps for recovering from corrupted images during RSU operations.

5.2. Guidelines for Performing Remote System Update Functions for Non-HPS

Guidelines for RSU functions without HPS host.

5.3. Commands and Responses

Explains command and response packets for SDM communication.

5.4. Quad SPI Flash Layout

Describes the layout of Quad SPI flash memory for RSU.

5.5. Generating Remote System Update Image Files Using the Programming File Generator

Generates RSU image files using the Programming File Generator tool.

5.6. Remote System Update from FPGA Core Example

Presents a complete RSU example, including image creation and programming.

6. Intel Agilex Configuration Features

6.1. Device Security

Outlines the security features of Intel Agilex devices.

6.2. Configuration via Protocol

Describes the CvP configuration scheme using PCIe.

6.3. Partial Reconfiguration

Explains Partial Reconfiguration (PR) for dynamic FPGA updates.

7. Intel Agilex Debugging Guide

7.1. Configuration Debugging Checklist

Checklist for identifying and resolving configuration issues.

7.3. Understanding Configuration Status Using quartus_pgm command

Using quartus_pgm command to check device configuration status.

7.8. Understanding and Troubleshooting Configuration Pin Behavior

Troubleshooting common configuration pin behaviors and failures.

8. Intel Agilex Configuration User Guide Archives

9. Document Revision History for the Intel Agilex Configuration User Guide