Intel Agilex Series User Manual

Figure 50. Components and Design Flow for JTAG Programming
Quartus Software flow on PC
Quartus Prime
Programmer
SOF
10 pin
JTAG header
Intel FPGA Download Cable II
Intel FPGA
SDM
PCB
Quartus Prime:
File Start Compile
Quartus Prime:
Tools Programming
Quartus Prime
Compilation
10 pin
3.3.2. JTAG Device Configuration
To configure a single device in a JTAG chain, the programming software sets the other devices to bypass mode. A device in
bypass mode transfers the programming data from the TDI pin to the TDO pin through a single bypass register. The
configuration data is available on the TDO pin one clock cycle later.
You can configure the Intel Agilex device through JTAG using a download cable or a microprocessor.
3. Intel Agilex Configuration Schemes
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Configuration User Guide
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Intel Agilex Series Specifications

General

Architecture	FPGA
AI Tensor Blocks	Yes
Category	FPGA
Family	Agilex
Transceiver Speed	Up to 112 Gbps
Manufacturer	Intel
Series	Agilex
Transceiver Data Rate	Up to 112 Gbps
Memory Support	HBM2E
PCIe Support	PCIe 5.0
Memory	HBM2e
Power Efficiency	Improved over previous generations
Operating Temperature	Commercial, Industrial
Process Technology	10nm