Intel Agilex Series

Figure 52. Connection Setup for JTAG Single-Device Configuration using a Microprocessor
Intel FPGA
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
OSC_CLK_1
MSEL[2:0]
TCK
ADDR DATA
Memory
Micro Processor
TDO
TDI
TMS
TCK
TDO
TDI
TMS
Configuration
Control Signals
JTAG
Configuration
Pins
Optional
Monitoring
10kΩ
Optional
MSEL
V
CCIO_SDM
3
JAM
Player
10kΩ
V
CCIO_SDM
Resistor values can vary between 1 kΩ to 10 kΩ.
Perform signal integrity analysis to select
the resistor value for your setup.
V
CCIO_SDM
R
DN
G
ND
R
UP
3.3.3. JTAG Multi-Device Configuration
You can configure multiple devices in a JTAG chain. Observe the following pin connections and guidelines for this configuration
setup:
3. Intel Agilex Configuration Schemes
683673 | 2021.10.29
Intel
®
Agilex
™
Configuration User Guide
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