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Intel Agilex Series User Manual

Intel Agilex Series
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Figure 9. Specify Configuration Scheme to Specify MSEL Value
Configuration
Scheme
2.5.3. Device Configuration Pins for Optional Configuration Signals
All configuration schemes use the same dedicated pins for the standard control signals shown in the Intel Agilex Configuration
Timing Diagram. Many other optional configuration signals do not have dedicated pin assignments.
Device Configuration Pins without Fixed Assignments
Note:
Although the CONF_DONE and INIT_DONE configuration signals are not required, Intel recommends that you use these
signals as an indicator to ensure that configuration is successful. The SDM drives the CONF_DONE signal high after
successfully receiving full bitstream. The SDM drives the INIT_DONE signal high to indicate the device is fully in user mode.
These signals are important when debugging configuration.
Table 6. Available SDM I/O Pin Assignments for Configuration Signals that Do Not Use Dedicated SDM I/O Pins
Signal Names
Configuration Scheme
Avalon-ST AS x4
x8 x16 x32
PWRMGT_SCL SDM_IO0 SDM_IO0
SDM_IO14
SDM_IO0
SDM_IO14
SDM_IO0
SDM_IO14
PWRMGT_SDA SDM_IO12
SDM_IO16
SDM_IO11
SDM_IO12
SDM_IO16
SDM_IO11
SDM_IO12
SDM_IO16
SDM_IO11
SDM_IO12
SDM_IO16
PWRMGT_ALERT SDM_IO0
SDM_IO9
SDM_IO12
SDM_IO0
SDM_IO9
SDM_IO12
SDM_IO0
SDM_IO12
SDM_IO0
SDM_IO12
continued...
2. Intel Agilex Configuration Details
683673 | 2021.10.29
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Intel
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Agilex
Configuration User Guide
31

Table of Contents

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Intel Agilex Series Specifications

General IconGeneral
ArchitectureFPGA
AI Tensor BlocksYes
CategoryFPGA
FamilyAgilex
Transceiver SpeedUp to 112 Gbps
ManufacturerIntel
SeriesAgilex
Transceiver Data RateUp to 112 Gbps
Memory SupportHBM2E
PCIe SupportPCIe 5.0
MemoryHBM2e
Power EfficiencyImproved over previous generations
Operating TemperatureCommercial, Industrial
Process Technology10nm

Summary

1. Intel Agilex Configuration User Guide

1.1. Intel Agilex Configuration Overview

Overview of Intel Agilex configuration, SDM, and schemes.

1.2. Intel Agilex Configuration Architecture

Details the Intel Agilex configuration architecture, including SDM, network, and LSMs.

2. Intel Agilex Configuration Details

2.1. Intel Agilex Configuration Timing Diagram

Timing diagram for power-on, configuration, and reconfiguration.

2.2. Configuration Flow Diagram

Describes the state transitions during Intel Agilex FPGA configuration.

2.5. Intel Agilex Configuration Pins

Details the configuration pins and their mapping for Intel Agilex devices.

2.6. Configuration Clocks

Covers configuration clock sources and requirements for Intel Agilex devices.

2.8. Generating Compressed .sof File

Generates a compressed .sof file to reduce size and improve configuration speed.

3. Intel Agilex Configuration Schemes

3.1. Avalon-ST Configuration

Describes the fast Avalon-ST configuration scheme using an external host.

3.1.1. Avalon-ST Configuration Scheme Hardware Components and File Types

Components and file types for implementing Avalon-ST configuration.

3.1.2. Enabling Avalon-ST Device Configuration

Steps to enable Avalon-ST configuration in Intel Quartus Prime.

3.1.6. Debugging Guidelines for the Avalon-ST Configuration Scheme

Debugging tips for the Avalon-ST configuration scheme.

3.2. AS Configuration

Details the AS configuration scheme using serial flash devices.

3.2.1. AS Configuration Scheme Hardware Components and File Types

Components and file types for the AS configuration scheme.

3.2.6. Programming Serial Flash Devices

Explains programming serial flash devices using AS interface.

3.2.9. Active Serial Configuration Software Settings

Software settings for AS configuration in Intel Quartus Prime.

3.2.10. Intel Quartus Prime Programming Steps

Steps for programming using Intel Quartus Prime.

3.2.11. Debugging Guidelines for the AS Configuration Scheme

Debugging tips for the AS configuration scheme.

4. Including the Reset Release Intel FPGA IP in Your Design

4.1. Understanding the Reset Release IP Requirement

Explains the necessity of the Reset Release IP for proper reset management.

4.5. Detailed Description of Device Configuration

Details device configuration steps including initialization.

5. Remote System Update (RSU)

5.1. Remote System Update Functional Description

Functional overview of Remote System Update (RSU) for Intel Agilex devices.

5.1.5. RSU Recovery from Corrupted Images

Provides steps for recovering from corrupted images during RSU operations.

5.3. Commands and Responses

Explains command and response packets for SDM communication.

5.4. Quad SPI Flash Layout

Describes the layout of Quad SPI flash memory for RSU.

5.5. Generating Remote System Update Image Files Using the Programming File Generator

Generates RSU image files using the Programming File Generator tool.

5.6. Remote System Update from FPGA Core Example

Presents a complete RSU example, including image creation and programming.

6. Intel Agilex Configuration Features

6.1. Device Security

Outlines the security features of Intel Agilex devices.

6.2. Configuration via Protocol

Describes the CvP configuration scheme using PCIe.

6.3. Partial Reconfiguration

Explains Partial Reconfiguration (PR) for dynamic FPGA updates.

7. Intel Agilex Debugging Guide

7.1. Configuration Debugging Checklist

Checklist for identifying and resolving configuration issues.

7.3. Understanding Configuration Status Using quartus_pgm command

Using quartus_pgm command to check device configuration status.

7.8. Understanding and Troubleshooting Configuration Pin Behavior

Troubleshooting common configuration pin behaviors and failures.

8. Intel Agilex Configuration User Guide Archives

9. Document Revision History for the Intel Agilex Configuration User Guide

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