Intel Agilex Series

Contents
1. Intel
®
Agilex
™
Configuration User Guide................................................................................................................................ 6
1.1. Intel
®
Agilex
™
Configuration Overview.............................................................................................................................6
1.1.1. Configuration and Related Signals.......................................................................................................................9
1.1.2. Intel Download Cables Supporting Configuration in Intel Agilex Devices..................................................................10
1.2. Intel Agilex Configuration Architecture...........................................................................................................................12
1.2.1. Secure Device Manager................................................................................................................................... 14
2. Intel Agilex Configuration Details........................................................................................................................................ 18
2.1. Intel Agilex Configuration Timing Diagram......................................................................................................................18
2.2. Configuration Flow Diagram......................................................................................................................................... 23
2.3. Device Response to Configuration and Reset Events.........................................................................................................26
2.4. Additional Clock Requirements for HPS and Transceivers................................................................................................. 26
2.5. Intel Agilex Configuration Pins...................................................................................................................................... 28
2.5.1. SDM Pin Mapping............................................................................................................................................28
2.5.2. MSEL Settings................................................................................................................................................ 29
2.5.3. Device Configuration Pins for Optional Configuration Signals................................................................................. 31
2.6. Configuration Clocks....................................................................................................................................................48
2.6.1. Setting Configuration Clock Source....................................................................................................................48
2.6.2. OSC_CLK_1 Clock Input...................................................................................................................................49
2.7. Intel Agilex Configuration Time Estimation..................................................................................................................... 50
2.8. Generating Compressed .sof File.................................................................................................................................51
3. Intel Agilex Configuration Schemes..................................................................................................................................... 53
3.1. Avalon-ST Configuration.............................................................................................................................................. 53
3.1.1. Avalon-ST Configuration Scheme Hardware Components and File Types ................................................................ 55
3.1.2. Enabling Avalon-ST Device Configuration............................................................................................................57
3.1.3. The AVST_READY Signal ................................................................................................................................. 57
3.1.4. RBF Configuration File Format...........................................................................................................................60
3.1.5. Avalon-ST Single-Device Configuration...............................................................................................................61
3.1.6. Debugging Guidelines for the Avalon-ST Configuration Scheme............................................................................. 64
3.1.7. IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core............................... 65
3.2. AS Configuration.......................................................................................................................................................102
Contents
Intel
®
Agilex
™
Configuration User Guide
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