Intel Agilex Series

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SDM Pins MSEL Function Configuration Source Function

Avalon-ST x8 AS x4

SDM_IO2

—

AVSTx8_DATA0 AS_CLK

SDM_IO3

—

AVSTx8_DATA3 AS_DATA2

SDM_IO4

—

AVSTx8_DATA1 AS_DATA0

SDM_IO5 MSEL0

—

AS_nCSOO

SDM_IO6

—

AVSTx8_DATA4 AS_DATA3

SDM_IO7 MSEL1

—

AS_nCSO2

SDM_IO8

—

AVSTx8_READY AS_nCSO3

SDM_IO9 MSEL2

—

AS_nCSO1

SDM_IO10

—

AVSTx8_DATA7

—

SDM_IO11

—

AVSTx8_VALID

—

SDM_IO12

— — —

SDM_IO13

—

AVSTx8_DATA5

—

SDM_IO14

—

AVSTx8_CLK

—

SDM_IO15

—

AVSTx8_DATA6 AS_nRST

SDM_IO16

— — —

2.5.2. MSEL Settings

After power-on MSEL[2:0] pins specify the configuration scheme for Intel Agilex devices. Use 4.7-kΩ resistors to pull the

MSEL[2:0] pins up to V

CCIO_SDM

or down to ground as required by the MSEL[2:0] setting for your configuration scheme.

2. Intel Agilex Configuration Details

683673 | 2021.10.29

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Intel

Agilex

™

Configuration User Guide

Main Page

Table of Contents2
Intel ® Agilex ™ Configuration User Guide6
Intel ® Agilex ™ Configuration Overview6
Configuration and Related Signals9
Intel Download Cables Supporting Configuration in Intel Agilex Devices10
Intel Agilex Configuration Architecture12
Secure Device Manager14
Intel Agilex Configuration Details18
Intel Agilex Configuration Timing Diagram18
Configuration Flow Diagram23
Device Response to Configuration and Reset Events26
Additional Clock Requirements for HPS and Transceivers26
Intel Agilex Configuration Pins28
SDM Pin Mapping28
MSEL Settings29
Device Configuration Pins for Optional Configuration Signals31
Configuration Clocks48
Setting Configuration Clock Source48
OSC_CLK_1 Clock Input49
Intel Agilex Configuration Time Estimation50
Generating Compressed .Sof File51
Intel Agilex Configuration Schemes53
Avalon-ST Configuration53
Avalon-ST Configuration Scheme Hardware Components and File Types55
Enabling Avalon-ST Device Configuration57
The AVST_READY Signal57
RBF Configuration File Format60
Avalon-ST Single-Device Configuration61
Debugging Guidelines for the Avalon-ST Configuration Scheme64
IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core65
AS Configuration102
AS Configuration Scheme Hardware Components and File Types103
AS Single-Device Configuration106
AS Using Multiple Serial Flash Devices107
AS Configuration Timing Parameters108
Maximum Allowable External AS_DATA Pin Skew Delay Guidelines109
Programming Serial Flash Devices110
Serial Flash Memory Layout114
As_Clk115
Active Serial Configuration Software Settings116
Intel Quartus Prime Programming Steps117
Debugging Guidelines for the as Configuration Scheme123
JTAG Configuration124
JTAG Configuration Scheme Hardware Components and File Types126
JTAG Device Configuration127
JTAG Multi-Device Configuration130
Debugging Guidelines for the JTAG Configuration Scheme132
Including the Reset Release Intel FPGA IP in Your Design134
Understanding the Reset Release IP Requirement135
Instantiating the Reset Release IP in Your Design137
Gating the PLL Reset Signal137
Guidance When Using Partial Reconfiguration (PR)138
Detailed Description of Device Configuration138
Device Initialization140
Preventing Register Initialization During Power-On140
Embedded Memory Block Initial Conditions142
Protecting State Machine Logic142
Remote System Update (RSU)144
Remote System Update Functional Description146
RSU Glossary146
Remote System Update Using as Configuration148
Remote System Update Configuration Images149
Remote System Update Configuration Sequence150
RSU Recovery from Corrupted Images151
Updates with the Factory Update Image154
Guidelines for Performing Remote System Update Functions for Non-HPS155
Commands and Responses156
Operation Commands158
Error Code Responses166
Error Code Recovery167
Quad SPI Flash Layout168
High Level Flash Layout168
Detailed Quad SPI Flash Layout175
Generating Remote System Update Image Files Using the Programming File Generator182
Generating the Initial RSU Image182
Generating an Application Image187
Generating a Factory Update Image189
Command Sequence to Perform Quad SPI Operations194
Remote System Update from FPGA Core Example194
Prerequisites195
Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image196
Programming Flash Memory with the Initial Remote System Update Image200
Reconfiguring the Device with an Application or Factory Image201
Adding an Application Image202
Removing an Application Image205
Intel Agilex Configuration Features207
Device Security207
Configuration Via Protocol207
Partial Reconfiguration209
Intel Agilex Debugging Guide210
Configuration Debugging Checklist210
Intel Agilex Configuration Architecture Overview212
Understanding Configuration Status Using Quartus_Pgm Command212
Configuration File Format Differences213
Understanding Seus214
Reading the Unique 64-Bit CHIP ID214
E-Tile Transceivers May Fail to Configure214
Understanding and Troubleshooting Configuration Pin Behavior215

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