4. Including the Reset Release Intel FPGA IP in Your Design
Intel requires that you either use the Reset Release Intel FPGA IP to hold your design in reset until configuration is complete.
The Reset Release Intel FPGA IP is available in the Intel Quartus Prime Software. This IP consists of a single output signal,
nINIT_DONE. The nINIT_DONE signal is the core version of the INIT_DONE pin and has the same function in both FPGA First
and HPS First configuration modes. Intel recommends that you hold your design in reset while the nINIT_DONE signal is high
or while the INIT_DONE pin is low. When you instantiate the Reset Release IP in your design, the SDM drives the
nINIT_DONE signal. Consequently, the IP does not consume any FPGA fabric resources, but does require routing resources.
Figure 54. Reset Release Intel FPGA IP nINIT_DONE Internal Connection
Board
nINIT_DONE
Reset
Application Logic
Intel FPGA
Reset Release IP
View the video guide below for a quick walk-through to understand the importance of using Reset Release Intel FPGA IP and
how to include it in your design.
683673 | 2021.10.29
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